System and method for an optimized winograd convolution accelerator

ABSTRACT

One embodiment provides a compute apparatus to perform machine learning operations, the compute apparatus comprising a hardware accelerator including a compute unit to perform a Winograd convolution, the compute unit configurable to perform the Winograd convolution for a first kernel size using a transform associated with a second kernel size.

CLAIM TO PRIORITY

This Application is a continuation of and claims the benefit of andpriority to U.S. application Ser. No. 15/670,359, entitled SYSTEM ANDMETHOD FOR AN OPTIMIZED WINOGRAD CONVOLUTION ACCELERATOR, by PradeepJanedula, et al., filed Aug. 7, 2017, the entire contents of which areincorporated herein by reference.

FIELD

Embodiments relate generally to data processing and more particularly tomachine learning processing via a general-purpose graphics processingunit.

BACKGROUND OF THE DESCRIPTION

Machine learning has been successful at solving many kinds of tasks. Thecomputations that arise when train and using machine learning algorithms(e.g., neural networks) lend themselves naturally to efficient parallelimplementations. Accordingly, parallel processors such asgeneral-purpose graphic processing units (GPGPUs) have played asignificant role in the practical implementation of deep neuralnetworks. However, implementing deep learning based machine learningsystems can require a large amount of memory and computing power. Deeplearning neural network models can be many megabytes in size and requirebillions of floating-point operations per second to efficiently process.Such requirements can prevent the deployment of many neural networkmodels to low power computing devices, such as devices suitable for usewithin the Internet of Things (IoT) application domain, which generallyconsists of low-end embedded devices

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the presentembodiments can be understood in detail, a more particular descriptionof the embodiments, briefly summarized above, may be had by reference toembodiments, some of which are illustrated in the appended drawings. Itis to be noted, however, that the appended drawings illustrate onlytypical embodiments and are therefore not to be considered limiting ofits scope.

FIG. 1 is a block diagram of a processing system, according to anembodiment;

FIG. 2 is a block diagram of a processor according to an embodiment;

FIG. 3 is a block diagram of a graphics processor, according to anembodiment;

FIG. 4 is a block diagram of a graphics processing engine of a graphicsprocessor in accordance with some embodiments;

FIG. 5 is a block diagram of hardware logic of a graphics processorcore, according to some embodiments described herein.

FIGS. 6A-6B illustrate thread execution logic including an array ofprocessing elements employed in a graphics processor core according toembodiments described herein.

FIG. 7 is a block diagram illustrating a graphics processor instructionformats according to some embodiments;

FIG. 8 is a block diagram of a graphics processor according to anotherembodiment.

FIG. 9A-9B illustrate a graphics processor command format and commandsequence, according to some embodiments;

FIG. 10 illustrates exemplary graphics software architecture for a dataprocessing system according to some embodiments;

FIG. 11 is a block diagram illustrating an IP core development system,according to an embodiment;

FIG. 12 is a block diagram illustrating an exemplary system on a chipintegrated circuit, according to an embodiment;

FIGS. 13A-13B are block diagrams illustrating exemplary graphicsprocessors for use within an SoC, according to embodiments describedherein.

FIG. 14 is a block diagram illustrating an additional exemplary graphicsprocessor of a system on a chip integrated circuit, according to anembodiment.

FIGS. 15A-15B illustrate Native and Winograd based 3D convolutions

FIG. 16 illustrates an architecture for 2D/3D convolutions based on theF[4,3] convolution.

FIG. 17 illustrates logic to generalize F(4,3) Winograd convolution tohigher order kernels.

FIG. 18 illustrates an exemplary logic and data layout to enablemulti-stride convolution, according to an embodiment.

FIG. 19 is a block diagram of a Winograd acceleration architectureaccording to embodiments described herein.

FIG. 20 illustrates input transform, according to an embodiment.

FIG. 21 illustrates an architecture for a Winograd compute block,according to an embodiment.

FIG. 22 illustrates logic configurable to perform native and optimizedweight transformation.

FIG. 23 illustrates an optimized Winograd weight transform architecture,according to an embodiment.

FIG. 24 illustrates a process to perform hardware-based Winogradconvolution using kernels of multiple sizes, according to embodimentsdescribed herein.

FIG. 25 illustrates a process to perform hardware-based Winogradconvolution using kernels of multiple strides, according to embodimentsdescribed herein.

FIG. 26 illustrates a process to perform optimized weight transformationfor hardware-based Winograd convolution, according to embodimentsdescribed herein.

FIG. 27 illustrates a machine learning software stack, according to anembodiment.

FIG. 28A-28B illustrate layers of exemplary deep neural networks.

FIG. 29 illustrates an exemplary recurrent neural network.

FIG. 30 illustrates training and deployment of a deep neural network.

FIG. 31 is a block diagram illustrating distributed learning.

DETAILED DESCRIPTION

In some embodiments, a graphics processing unit (GPU) is communicativelycoupled to host/processor cores to accelerate graphics operations,machine-learning operations, pattern analysis operations, and variousgeneral-purpose GPU (GPGPU) functions. The GPU may be communicativelycoupled to the host processor/cores over a bus or another interconnect.In other embodiments, the GPU may be integrated on the same package orchip as the cores and communicatively coupled to the cores over aninternal processor bus/interconnect (i.e., internal to the package orchip). Regardless of the manner in which the GPU is connected, theprocessor cores may allocate work to the GPU in the form of sequences ofcommands/instructions contained in a work descriptor. The GPU then usesdedicated circuitry/logic for efficiently processing thesecommands/instructions.

In the description that follows, FIGS. 1-14 provide an overview ofexemplary data processing system and graphics processor logic thatincorporates or relates to the various embodiments. FIGS. 15-26 providespecific details of the various embodiments. FIGS. 27-31 provide anoverview of machine learning hardware and software architecture. Someaspects of the following embodiments are described with reference to agraphics processor, while other aspects are described with respect to ageneral-purpose processor, such as a central processing unit (CPU).Similar techniques and teachings can be applied to other types ofcircuits or semiconductor devices, including but not limited to a manyintegrated core processor, a GPU cluster, or one or more instances of afield programmable gate array (FPGA). In general, the teachings areapplicable to any processor or machine that manipulates or processesimage (e.g., sample, pixel), vertex data, or geometry data. Theembodiments described herein may be practiced without one or more of thespecific details provided herein. In some instances, well-known featureshave not been described to avoid obscuring the details of the presentembodiments.

System Overview

FIG. 1 is a block diagram of a processing system 100, according to anembodiment. In various embodiments the system 100 includes one or moreprocessors 102 and one or more graphics processors 108, and may be asingle processor desktop system, a multiprocessor workstation system, ora server system having a large number of processors 102 or processorcores 107. In one embodiment, the system 100 is a processing platformincorporated within a system-on-a-chip (SoC) integrated circuit for usein mobile, handheld, or embedded devices.

In one embodiment the system 100 can include, or be incorporated withina server-based gaming platform, a game console, including a game andmedia console, a mobile gaming console, a handheld game console, or anonline game console. In some embodiments the system 100 is a mobilephone, smart phone, tablet computing device or mobile Internet device.The processing system 100 can also include, couple with, or beintegrated within a wearable device, such as a smart watch wearabledevice, smart eyewear device, augmented reality device, or virtualreality device. In some embodiments, the processing system 100 is atelevision or set top box device having one or more processors 102 and agraphical interface generated by one or more graphics processors 108.

In some embodiments, the one or more processors 102 each include one ormore processor cores 107 to process instructions which, when executed,perform operations for system and user software. In some embodiments,each of the one or more processor cores 107 is configured to process aspecific instruction set 109. In some embodiments, instruction set 109may facilitate Complex Instruction Set Computing (CISC), ReducedInstruction Set Computing (RISC), or computing via a Very LongInstruction Word (VLIW). Multiple processor cores 107 may each process adifferent instruction set 109, which may include instructions tofacilitate the emulation of other instruction sets. Processor core 107may also include other processing devices, such a Digital SignalProcessor (DSP).

In some embodiments, the processor 102 includes cache memory 104.Depending on the architecture, the processor 102 can have a singleinternal cache or multiple levels of internal cache. In someembodiments, the cache memory is shared among various components of theprocessor 102. In some embodiments, the processor 102 also uses anexternal cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC))(not shown), which may be shared among processor cores 107 using knowncache coherency techniques. A register file 106 is additionally includedin processor 102 which may include different types of registers forstoring different types of data (e.g., integer registers, floating pointregisters, status registers, and an instruction pointer register). Someregisters may be general-purpose registers, while other registers may bespecific to the design of the processor 102.

In some embodiments, one or more processor(s) 102 are coupled with aprocessor bus 110 to transmit communication signals such as address,data, or control signals between processor 102 and other components inthe system 100. The processor bus 110, in one embodiment, is a versionof the Direct Media Interface (DMI) bus. In one embodiment theprocessor(s) 102 include an integrated memory controller 116 and aperipheral controller 130. The memory controller 116 facilitatescommunication between a memory device and other components of the system100, while the peripheral controller hub (PCH) 130 provides connectionsto I/O devices via a local I/O bus.

The memory device 120 can be a dynamic random access memory (DRAM)device, a static random access memory (SRAM) device, flash memorydevice, phase-change memory device, or some other memory device havingsuitable performance to serve as process memory. In one embodiment thememory device 120 can operate as system memory for the system 100, tostore data 122 and instructions 121 for use when the one or moreprocessors 102 executes an application or process. Memory controller 116also couples with an optional external graphics processor 112, which maycommunicate with the one or more graphics processors 108 in processors102 to perform graphics and media operations. In some embodiments adisplay device 111 can connect to the processor(s) 102. The displaydevice 111 can be one or more of an internal display device, as in amobile electronic device or a laptop device or an external displaydevice attached via a display interface (e.g., DisplayPort, etc.). Inone embodiment the display device 111 can be a head mounted display(HMD) such as a stereoscopic display device for use in virtual reality(VR) applications or augmented reality (AR) applications.

In some embodiments the peripheral controller 130 enables peripherals toconnect to memory device 120 and processor 102 via a high-speed I/O bus.The I/O peripherals include, but are not limited to, an audio controller146, a network controller 134, a firmware interface 128, a wirelesstransceiver 126, touch sensors 125, a data storage device 124 (e.g.,hard disk drive, flash memory, etc.). The data storage device 124 canconnect via a storage interface (e.g., SATA) or via a peripheral bus,such as a Peripheral Component Interconnect bus (e.g., PCI, PCIExpress). The touch sensors 125 can include touch screen sensors,pressure sensors, or fingerprint sensors. The wireless transceiver 126can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile networktransceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver.The firmware interface 128 enables communication with system firmware,and can be, for example, a unified extensible firmware interface (UEFI).The network controller 134 can enable a network connection to a wirednetwork. In some embodiments, a high-performance network controller (notshown) couples with the processor bus 110. The audio controller 146, inone embodiment, is a multi-channel high definition audio controller. Inone embodiment the system 100 incudes an optional legacy I/O controller140 for coupling legacy (e.g., Personal System 2 (PS/2)) devices to thesystem. The peripheral controller 130 can also connect to one or moreUniversal Serial Bus (USB) controllers 142 connect input devices, suchas keyboard and mouse 143 combinations, a camera 144, or other USB inputdevices.

It will be appreciated that the system 100 shown is exemplary and notlimiting, as other types of data processing systems that are differentlyconfigured may also be used. For example, an instance of the memorycontroller 116 and peripheral controller 130 may be integrated into adiscreet external graphics processor, such as the external graphicsprocessor 112. In one embodiment the peripheral controller 130 and/ormemory controller 1160 may be external to the one or more processor(s)102. For example, the system 100 can include an external memorycontroller 116 and peripheral controller 130, which may be configured asa memory controller hub and peripheral controller hub within a systemchipset that is in communication with the processor(s) 102.

FIG. 2 is a block diagram of an embodiment of a processor 200 having oneor more processor cores 202A-202N, an integrated memory controller 214,and an integrated graphics processor 208. Those elements of FIG. 2having the same reference numbers (or names) as the elements of anyother figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such. Processor200 can include additional cores up to and including additional core202N represented by the dashed lined boxes. Each of processor cores202A-202N includes one or more internal cache units 204A-204N. In someembodiments each processor core also has access to one or more sharedcached units 206.

The internal cache units 204A-204N and shared cache units 206 representa cache memory hierarchy within the processor 200. The cache memoryhierarchy may include at least one level of instruction and data cachewithin each processor core and one or more levels of shared mid-levelcache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or otherlevels of cache, where the highest level of cache before external memoryis classified as the LLC. In some embodiments, cache coherency logicmaintains coherency between the various cache units 206 and 204A-204N.

In some embodiments, processor 200 may also include a set of one or morebus controller units 216 and a system agent core 210. The one or morebus controller units 216 manage a set of peripheral buses, such as oneor more PCI or PCI express busses. System agent core 210 providesmanagement functionality for the various processor components. In someembodiments, system agent core 210 includes one or more integratedmemory controllers 214 to manage access to various external memorydevices (not shown).

In some embodiments, one or more of the processor cores 202A-202Ninclude support for simultaneous multi-threading. In such embodiment,the system agent core 210 includes components for coordinating andoperating cores 202A-202N during multi-threaded processing. System agentcore 210 may additionally include a power control unit (PCU), whichincludes logic and components to regulate the power state of processorcores 202A-202N and graphics processor 208.

In some embodiments, processor 200 additionally includes graphicsprocessor 208 to execute graphics processing operations. In someembodiments, the graphics processor 208 couples with the set of sharedcache units 206, and the system agent core 210, including the one ormore integrated memory controllers 214. In some embodiments, the systemagent core 210 also includes a display controller 211 to drive graphicsprocessor output to one or more coupled displays. In some embodiments,display controller 211 may also be a separate module coupled with thegraphics processor via at least one interconnect, or may be integratedwithin the graphics processor 208.

In some embodiments, a ring based interconnect unit 212 is used tocouple the internal components of the processor 200. However, analternative interconnect unit may be used, such as a point-to-pointinterconnect, a switched interconnect, or other techniques, includingtechniques well known in the art. In some embodiments, graphicsprocessor 208 couples with the ring interconnect 212 via an I/O link213.

The exemplary I/O link 213 represents at least one of multiple varietiesof I/O interconnects, including an on package I/O interconnect whichfacilitates communication between various processor components and ahigh-performance embedded memory module 218, such as an eDRAM module. Insome embodiments, each of the processor cores 202A-202N and graphicsprocessor 208 use embedded memory modules 218 as a shared Last LevelCache.

In some embodiments, processor cores 202A-202N are homogenous coresexecuting the same instruction set architecture. In another embodiment,processor cores 202A-202N are heterogeneous in terms of instruction setarchitecture (ISA), where one or more of processor cores 202A-202Nexecute a first instruction set, while at least one of the other coresexecutes a subset of the first instruction set or a differentinstruction set. In one embodiment processor cores 202A-202N areheterogeneous in terms of microarchitecture, where one or more coreshaving a relatively higher power consumption couple with one or morepower cores having a lower power consumption. Additionally, processor200 can be implemented on one or more chips or as an SoC integratedcircuit having the illustrated components, in addition to othercomponents.

FIG. 3 is a block diagram of a graphics processor 300, which may be adiscrete graphics processing unit, or may be a graphics processorintegrated with a plurality of processing cores. In some embodiments,the graphics processor communicates via a memory mapped I/O interface toregisters on the graphics processor and with commands placed into theprocessor memory. In some embodiments, graphics processor 300 includes amemory interface 314 to access memory. Memory interface 314 can be aninterface to local memory, one or more internal caches, one or moreshared external caches, and/or to system memory.

In some embodiments, graphics processor 300 also includes a displaycontroller 302 to drive display output data to a display device 320.Display controller 302 includes hardware for one or more overlay planesfor the display and composition of multiple layers of video or userinterface elements. The display device 320 can be an internal orexternal display device. In one embodiment the display device 320 is ahead mounted display device, such as a virtual reality (VR) displaydevice or an augmented reality (AR) display device. In some embodiments,graphics processor 300 includes a video codec engine 306 to encode,decode, or transcode media to, from, or between one or more mediaencoding formats, including, but not limited to Moving Picture ExpertsGroup (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formatssuch as H.264/MPEG-4 AVC, as well as the Society of Motion Picture &Television Engineers (SMPTE) 421M/VC-1, and Joint Photographic ExpertsGroup (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats.

In some embodiments, graphics processor 300 includes a block imagetransfer (BLIT) engine 304 to perform two-dimensional (2D) rasterizeroperations including, for example, bit-boundary block transfers.However, in one embodiment, 2D graphics operations are performed usingone or more components of graphics processing engine (GPE) 310. In someembodiments, GPE 310 is a compute engine for performing graphicsoperations, including three-dimensional (3D) graphics operations andmedia operations.

In some embodiments, GPE 310 includes a 3D pipeline 312 for performing3D operations, such as rendering three-dimensional images and scenesusing processing functions that act upon 3D primitive shapes (e.g.,rectangle, triangle, etc.). The 3D pipeline 312 includes programmableand fixed function elements that perform various tasks within theelement and/or spawn execution threads to a 3D/Media sub-system 315.While 3D pipeline 312 can be used to perform media operations, anembodiment of GPE 310 also includes a media pipeline 316 that isspecifically used to perform media operations, such as videopost-processing and image enhancement.

In some embodiments, media pipeline 316 includes fixed function orprogrammable logic units to perform one or more specialized mediaoperations, such as video decode acceleration, video de-interlacing, andvideo encode acceleration in place of, or on behalf of video codecengine 306. In some embodiments, media pipeline 316 additionallyincludes a thread spawning unit to spawn threads for execution on3D/Media sub-system 315. The spawned threads perform computations forthe media operations on one or more graphics execution units included in3D/Media sub-system 315.

In some embodiments, 3D/Media subsystem 315 includes logic for executingthreads spawned by 3D pipeline 312 and media pipeline 316. In oneembodiment, the pipelines send thread execution requests to 3D/Mediasubsystem 315, which includes thread dispatch logic for arbitrating anddispatching the various requests to available thread executionresources. The execution resources include an array of graphicsexecution units to process the 3D and media threads. In someembodiments, 3D/Media subsystem 315 includes one or more internal cachesfor thread instructions and data. In some embodiments, the subsystemalso includes shared memory, including registers and addressable memory,to share data between threads and to store output data.

Graphics Processing Engine

FIG. 4 is a block diagram of a graphics processing engine 410 of agraphics processor in accordance with some embodiments. In oneembodiment, the graphics processing engine (GPE) 410 is a version of theGPE 310 shown in FIG. 3. Elements of FIG. 4 having the same referencenumbers (or names) as the elements of any other figure herein canoperate or function in any manner similar to that described elsewhereherein, but are not limited to such. For example, the 3D pipeline 312and media pipeline 316 of FIG. 3 are illustrated. The media pipeline 316is optional in some embodiments of the GPE 410 and may not be explicitlyincluded within the GPE 410. For example and in at least one embodiment,a separate media and/or image processor is coupled to the GPE 410.

In some embodiments, GPE 410 couples with or includes a command streamer403, which provides a command stream to the 3D pipeline 312 and/or mediapipelines 316. In some embodiments, command streamer 403 is coupled withmemory, which can be system memory, or one or more of internal cachememory and shared cache memory. In some embodiments, command streamer403 receives commands from the memory and sends the commands to 3Dpipeline 312 and/or media pipeline 316. The commands are directivesfetched from a ring buffer, which stores commands for the 3D pipeline312 and media pipeline 316. In one embodiment, the ring buffer canadditionally include batch command buffers storing batches of multiplecommands. The commands for the 3D pipeline 312 can also includereferences to data stored in memory, such as but not limited to vertexand geometry data for the 3D pipeline 312 and/or image data and memoryobjects for the media pipeline 316. The 3D pipeline 312 and mediapipeline 316 process the commands and data by performing operations vialogic within the respective pipelines or by dispatching one or moreexecution threads to a graphics core array 414. In one embodiment thegraphics core array 414 include one or more blocks of graphics cores(e.g., graphics core(s) 415A, graphics core(s) 415B), each blockincluding one or more graphics cores. Each graphics core includes a setof graphics execution resources that includes general purpose andgraphics specific execution logic to perform graphics and computeoperations, as well as fixed function texture processing and/or machinelearning and artificial intelligence acceleration logic.

In various embodiments the 3D pipeline 312 includes fixed function andprogrammable logic to process one or more shader programs, such asvertex shaders, geometry shaders, pixel shaders, fragment shaders,compute shaders, or other shader programs, by processing theinstructions and dispatching execution threads to the graphics corearray 414. The graphics core array 414 provides a unified block ofexecution resources for use in processing these shader programs.Multi-purpose execution logic (e.g., execution units) within thegraphics core(s) 415A-414B of the graphic core array 414 includessupport for various 3D API shader languages and can execute multiplesimultaneous execution threads associated with multiple shaders.

In some embodiments the graphics core array 414 also includes executionlogic to perform media functions, such as video and/or image processing.In one embodiment, the execution units additionally includegeneral-purpose logic that is programmable to perform parallel generalpurpose computational operations, in addition to graphics processingoperations. The general purpose logic can perform processing operationsin parallel or in conjunction with general purpose logic within theprocessor core(s) 107 of FIG. 1 or core 202A-202N as in FIG. 2.

Output data generated by threads executing on the graphics core array414 can output data to memory in a unified return buffer (URB) 418. TheURB 418 can store data for multiple threads. In some embodiments the URB418 may be used to send data between different threads executing on thegraphics core array 414. In some embodiments the URB 418 mayadditionally be used for synchronization between threads on the graphicscore array and fixed function logic within the shared function logic420.

In some embodiments, graphics core array 414 is scalable, such that thearray includes a variable number of graphics cores, each having avariable number of execution units based on the target power andperformance level of GPE 410. In one embodiment the execution resourcesare dynamically scalable, such that execution resources may be enabledor disabled as needed.

The graphics core array 414 couples with shared function logic 420 thatincludes multiple resources that are shared between the graphics coresin the graphics core array. The shared functions within the sharedfunction logic 420 are hardware logic units that provide specializedsupplemental functionality to the graphics core array 414. In variousembodiments, shared function logic 420 includes but is not limited tosampler 421, math 422, and inter-thread communication (ITC) 423 logic.Additionally, some embodiments implement one or more cache(s) 425 withinthe shared function logic 420.

A shared function is implemented where the demand for a givenspecialized function is insufficient for inclusion within the graphicscore array 414. Instead a single instantiation of that specializedfunction is implemented as a stand-alone entity in the shared functionlogic 420 and shared among the execution resources within the graphicscore array 414. The precise set of functions that are shared between thegraphics core array 414 and included within the graphics core array 414varies across embodiments. In some embodiments, specific sharedfunctions within the shared function logic 420 that are used extensivelyby the graphics core array 414 may be included within shared functionlogic 416 within the graphics core array 414. In various embodiments,the shared function logic 416 within the graphics core array 414 caninclude some or all logic within the shared function logic 420. In oneembodiment, all logic elements within the shared function logic 420 maybe duplicated within the shared function logic 416 of the graphics corearray 414. In one embodiment the shared function logic 420 is excludedin favor of the shared function logic 416 within the graphics core array414.

FIG. 5 is a block diagram of hardware logic of a graphics processor core500, according to some embodiments described herein. Elements of FIG. 5having the same reference numbers (or names) as the elements of anyother figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such. Theillustrated graphics processor core 500, in some embodiments, isincluded within the graphics core array 414 of FIG. 4. The graphicsprocessor core 500, sometimes referred to as a core slice, can be one ormultiple graphics cores within a modular graphics processor. Thegraphics processor core 500 is exemplary of one graphics core slice, anda graphics processor as described herein may include multiple graphicscore slices based on target power and performance envelopes. Eachgraphics core 500 can include a fixed function block 530 coupled withmultiple sub-cores 501A-501F, also referred to as sub-slices, thatinclude modular blocks of general purpose and fixed function logic.

In some embodiments the fixed function block 530 includes ageometry/fixed function pipeline 536 that can be shared by all sub-coresin the graphics processor 500, for example, in lower performance and/orlower power graphics processor implementations. In various embodiments,the geometry/fixed function pipeline 536 includes a 3D fixed functionpipeline (e.g., 3D pipeline 312 as in FIG. 3 and FIG. 4) a videofront-end unit, a thread spawner and thread dispatcher, and a unifiedreturn buffer manager, which manages unified return buffers, such as theunified return buffer 418 of FIG. 4.

In one embodiment the fixed function block 530 also includes a graphicsSoC interface 537, a graphics microcontroller 538, and a media pipeline539. The graphics SoC interface 537 provides an interface between thegraphics core 500 and other processor cores within a system on a chipintegrated circuit. The graphics microcontroller 538 is a programmablesub-processor that is configurable to manage various functions of thegraphics processor 500, including thread dispatch, scheduling, andpre-emption. The media pipeline 539 (e.g., media pipeline 316 of FIG. 3and FIG. 4) includes logic to facilitate the decoding, encoding,pre-processing, and/or post-processing of multimedia data, includingimage and video data. The media pipeline 539 implement media operationsvia requests to compute or sampling logic within the sub-cores 501-501F.

In one embodiment the SoC interface 537 enables the graphics core 500 tocommunicate with general purpose application processor cores (e.g.,CPUs) and/or other components within an SoC, including memory hierarchyelements such as a shared last level cache memory, the system RAM,and/or embedded on-chip or on-package DRAM. The SoC interface 537 canalso enable communication with fixed function devices within the SoC,such as camera imaging pipelines, and enables the use of and/orimplements global memory atomics that may be shared between the graphicscore 500 and CPUs within the SoC. The SoC interface 537 can alsoimplement power management controls for the graphics core 500 and enablean interface between a clock domain of the graphic core 500 and otherclock domains within the SoC. In one embodiment the SoC interface 537enables receipt of command buffers from a command streamer and globalthread dispatcher that are configured to provide commands andinstructions to each of one or more graphics cores within a graphicsprocessor. The commands and instructions can be dispatched to the mediapipeline 539, when media operations are to be performed, or a geometryand fixed function pipeline (e.g., geometry and fixed function pipeline536, geometry and fixed function pipeline 514) when graphics processingoperations are to be performed.

The graphics microcontroller 538 can be configured to perform variousscheduling and management tasks for the graphics core 500. In oneembodiment the graphics microcontroller 538 can perform graphics and/orcompute workload scheduling on the various graphics parallel engineswithin execution unit (EU) arrays 502A-502F, 504A-504F within thesub-cores 501A-501F. In this scheduling model, host software executingon a CPU core of an SoC including the graphics core 500 can submitworkloads one of multiple graphic processor doorbells, which invokes ascheduling operation on the appropriate graphics engine. Schedulingoperations include determining which workload to run next, submitting aworkload to a command streamer, pre-empting existing workloads runningon an engine, monitoring progress of a workload, and notifying hostsoftware when a workload is complete. In one embodiment the graphicsmicrocontroller 538 can also facilitate low-power or idle states for thegraphics core 500, providing the graphics core 500 with the ability tosave and restore registers within the graphics core 500 across low-powerstate transitions independently from the operating system and/orgraphics driver software on the system.

The graphics core 500 may have greater than or fewer than theillustrated sub-cores 501A-501F, up to N modular sub-cores. For each setof N sub-cores, the graphics core 500 can also include shared functionlogic 510, shared and/or cache memory 512, a geometry/fixed functionpipeline 514, as well as additional fixed function logic 516 toaccelerate various graphics and compute processing operations. Theshared function logic 510 can include logic units associated with theshared function logic 420 of FIG. 4 (e.g., sampler, math, and/orinter-thread communication logic) that can be shared by each N sub-coreswithin the graphics core 500. The shared and/or cache memory 512 can bea last-level cache for the set of N sub-cores 501A-501F within thegraphics core 500, and can also serve as shared memory that isaccessible by multiple sub-cores. The geometry/fixed function pipeline514 can be included instead of the geometry/fixed function pipeline 536within the fixed function block 530 and can include the same or similarlogic units.

In one embodiment the graphics core 500 includes additional fixedfunction logic 516 that can include various fixed function accelerationlogic for use by the graphics core 500. In one embodiment the additionalfixed function logic 516 includes an additional geometry pipeline foruse in position only shading. In position-only shading, two geometrypipelines exist, the full geometry pipeline within the geometry/fixedfunction pipeline 516, 536, and a cull pipeline, which is an additionalgeometry pipeline which may be included within the additional fixedfunction logic 516. In one embodiment the cull pipeline is a trimmeddown version of the full geometry pipeline. The full pipeline and thecull pipeline can execute different instances of the same application,each instance having a separate context. Position only shading can hidelong cull runs of discarded triangles, enabling shading to be completedearlier in some instances. For example and in one embodiment the cullpipeline logic within the additional fixed function logic 516 canexecute position shaders in parallel with the main application andgenerally generates critical results faster than the full pipeline, asthe cull pipeline fetches and shades only the position attribute of thevertices, without performing rasterization and rendering of the pixelsto the frame buffer. The cull pipeline can use the generated criticalresults to compute visibility information for all the triangles withoutregard to whether those triangles are culled. The full pipeline (whichin this instance may be referred to as a replay pipeline) can consumethe visibility information to skip the culled triangles to shade onlythe visible triangles that are finally passed to the rasterizationphase.

In one embodiment the additional fixed function logic 516 can alsoinclude machine-learning acceleration logic, such as fixed functionmatrix multiplication logic, for implementations including optimizationsfor machine learning training or inferencing.

Within each graphics sub-core 501A-501F includes a set of executionresources that may be used to perform graphics, media, and computeoperations in response to requests by graphics pipeline, media pipeline,or shader programs. The graphics sub-cores 501A-501F include multiple EUarrays 502A-502F, 504A-504F, thread dispatch and inter-threadcommunication (TD/IC) logic 503A-503F, a 3D (e.g., texture) sampler505A-505F, a media sampler 506A-506F, a shader processor 507A-507F, andshared local memory (SLM) 508A-508F. The EU arrays 502A-502F, 504A-504Feach include multiple execution units, which are general-purposegraphics processing units capable of performing floating-point andinteger/fixed-point logic operations in service of a graphics, media, orcompute operation, including graphics, media, or compute shaderprograms. The TD/IC logic 503A-503F performs local thread dispatch andthread control operations for the execution units within a sub-core andfacilitate communication between threads executing on the executionunits of the sub-core. The 3D sampler 505A-505F can read texture orother 3D graphics related data into memory. The 3D sampler can readtexture data differently based on a configured sample state and thetexture format associated with a given texture. The media sampler506A-506F can perform similar read operations based on the type andformat associated with media data. In one embodiment, each graphicssub-core 501A-501F can alternately include a unified 3D and mediasampler. Threads executing on the execution units within each of thesub-cores 501A-501F can make use of shared local memory 508A-508F withineach sub-core, to enable threads executing within a thread group toexecute using a common pool of on-chip memory.

Execution Units

FIGS. 6A-6B illustrate thread execution logic 600 including an array ofprocessing elements employed in a graphics processor core according toembodiments described herein. Elements of FIGS. 6A-6B having the samereference numbers (or names) as the elements of any other figure hereincan operate or function in any manner similar to that describedelsewhere herein, but are not limited to such. FIG. 6A illustrates anoverview of thread execution logic 600, which can include a variant ofthe hardware logic illustrated with each sub-core 501A-501F of FIG. 5.FIG. 6B illustrates exemplary internal details of an execution unit.

As illustrated in FIG. 6A, in some embodiments thread execution logic600 includes a shader processor 602, a thread dispatcher 604,instruction cache 606, a scalable execution unit array including aplurality of execution units 608A-608N, a sampler 610, a data cache 612,and a data port 614. In one embodiment the scalable execution unit arraycan dynamically scale by enabling or disabling one or more executionunits (e.g., any of execution unit 608A, 608B, 608C, 608D, through608N-1 and 608N) based on the computational requirements of a workload.In one embodiment the included components are interconnected via aninterconnect fabric that links to each of the components. In someembodiments, thread execution logic 600 includes one or more connectionsto memory, such as system memory or cache memory, through one or more ofinstruction cache 606, data port 614, sampler 610, and execution units608A-608N. In some embodiments, each execution unit (e.g. 608A) is astand-alone programmable general purpose computational unit that iscapable of executing multiple simultaneous hardware threads whileprocessing multiple data elements in parallel for each thread. Invarious embodiments, the array of execution units 608A-608N is scalableto include any number individual execution units.

In some embodiments, the execution units 608A-608N are primarily used toexecute shader programs. A shader processor 602 can process the variousshader programs and dispatch execution threads associated with theshader programs via a thread dispatcher 604. In one embodiment thethread dispatcher includes logic to arbitrate thread initiation requestsfrom the graphics and media pipelines and instantiate the requestedthreads on one or more execution unit in the execution units 608A-608N.For example, a geometry pipeline can dispatch vertex, tessellation, orgeometry shaders to the thread execution logic for processing. In someembodiments, thread dispatcher 604 can also process runtime threadspawning requests from the executing shader programs.

In some embodiments, the execution units 608A-608N support aninstruction set that includes native support for many standard 3Dgraphics shader instructions, such that shader programs from graphicslibraries (e.g., Direct 3D and OpenGL) are executed with a minimaltranslation. The execution units support vertex and geometry processing(e.g., vertex programs, geometry programs, vertex shaders), pixelprocessing (e.g., pixel shaders, fragment shaders) and general-purposeprocessing (e.g., compute and media shaders). Each of the executionunits 608A-608N is capable of multi-issue single instruction multipledata (SIMD) execution and multi-threaded operation enables an efficientexecution environment in the face of higher latency memory accesses.Each hardware thread within each execution unit has a dedicatedhigh-bandwidth register file and associated independent thread-state.Execution is multi-issue per clock to pipelines capable of integer,single and double precision floating point operations, SIMD branchcapability, logical operations, transcendental operations, and othermiscellaneous operations. While waiting for data from memory or one ofthe shared functions, dependency logic within the execution units608A-608N causes a waiting thread to sleep until the requested data hasbeen returned. While the waiting thread is sleeping, hardware resourcesmay be devoted to processing other threads. For example, during a delayassociated with a vertex shader operation, an execution unit can performoperations for a pixel shader, fragment shader, or another type ofshader program, including a different vertex shader.

Each execution unit in execution units 608A-608N operates on arrays ofdata elements. The number of data elements is the “execution size,” orthe number of channels for the instruction. An execution channel is alogical unit of execution for data element access, masking, and flowcontrol within instructions. The number of channels may be independentof the number of physical Arithmetic Logic Units (ALUs) or FloatingPoint Units (FPUs) for a particular graphics processor. In someembodiments, execution units 608A-608N support integer andfloating-point data types.

The execution unit instruction set includes SIMD instructions. Thevarious data elements can be stored as a packed data type in a registerand the execution unit will process the various elements based on thedata size of the elements. For example, when operating on a 256-bit widevector, the 256 bits of the vector are stored in a register and theexecution unit operates on the vector as four separate 64-bit packeddata elements (Quad-Word (QW) size data elements), eight separate 32-bitpacked data elements (Double Word (DW) size data elements), sixteenseparate 16-bit packed data elements (Word (W) size data elements), orthirty-two separate 8-bit data elements (byte (B) size data elements).However, different vector widths and register sizes are possible.

In one embodiment one or more execution units can be combined into afused execution unit 609A-609N having thread control logic (607A-607N)that is common to the fused EUs. Multiple EUs can be fused into an EUgroup. Each EU in the fused EU group can be configured to execute aseparate SIMD hardware thread. The number of EUs in a fused EU group canvary according to embodiments. Additionally, various SIMD widths can beperformed per-EU, including but not limited to SIMD8, SIMD16, andSIMD32. Each fused graphics execution unit 609A-609N includes at leasttwo execution units. For example, fused execution unit 609A includes afirst EU 608A, second EU 608B, and thread control logic 607A that iscommon to the first EU 608A and the second EU 608B. The thread controllogic 607A controls threads executed on the fused graphics executionunit 609A, allowing each EU within the fused execution units 609A-609Nto execute using a common instruction pointer register.

One or more internal instruction caches (e.g., 606) are included in thethread execution logic 600 to cache thread instructions for theexecution units. In some embodiments, one or more data caches (e.g.,612) are included to cache thread data during thread execution. In someembodiments, a sampler 610 is included to provide texture sampling for3D operations and media sampling for media operations. In someembodiments, sampler 610 includes specialized texture or media samplingfunctionality to process texture or media data during the samplingprocess before providing the sampled data to an execution unit.

During execution, the graphics and media pipelines send threadinitiation requests to thread execution logic 600 via thread spawningand dispatch logic. Once a group of geometric objects has been processedand rasterized into pixel data, pixel processor logic (e.g., pixelshader logic, fragment shader logic, etc.) within the shader processor602 is invoked to further compute output information and cause resultsto be written to output surfaces (e.g., color buffers, depth buffers,stencil buffers, etc.). In some embodiments, a pixel shader or fragmentshader calculates the values of the various vertex attributes that areto be interpolated across the rasterized object. In some embodiments,pixel processor logic within the shader processor 602 then executes anapplication programming interface (API)-supplied pixel or fragmentshader program. To execute the shader program, the shader processor 602dispatches threads to an execution unit (e.g., 608A) via threaddispatcher 604. In some embodiments, shader processor 602 uses texturesampling logic in the sampler 610 to access texture data in texture mapsstored in memory. Arithmetic operations on the texture data and theinput geometry data compute pixel color data for each geometricfragment, or discards one or more pixels from further processing.

In some embodiments, the data port 614 provides a memory accessmechanism for the thread execution logic 600 to output processed data tomemory for further processing on a graphics processor output pipeline.In some embodiments, the data port 614 includes or couples to one ormore cache memories (e.g., data cache 612) to cache data for memoryaccess via the data port.

As illustrated in FIG. 6B, a graphics execution unit 608 can include aninstruction fetch unit 637, a general register file array (GRF) 624, anarchitectural register file array (ARF) 626, a thread arbiter 622, asend unit 630, a branch unit 632, a set of SIMD floating point units(FPUs) 634, and in one embodiment a set of dedicated integer SIMD ALUs635. The GRF 624 and ARF 626 includes the set of general register filesand architecture register files associated with each simultaneoushardware thread that may be active in the graphics execution unit 608.In one embodiment, per thread architectural state is maintained in theARF 626, while data used during thread execution is stored in the GRF624. The execution state of each thread, including the instructionpointers for each thread, can be held in thread-specific registers inthe ARF 626.

In one embodiment the graphics execution unit 608 has an architecturethat is a combination of Simultaneous Multi-Threading (SMT) andfine-grained Interleaved Multi-Threading (IMT). The architecture has amodular configuration that can be fine tuned at design time based on atarget number of simultaneous threads and number of registers perexecution unit, where execution unit resources are divided across logicused to execute multiple simultaneous threads.

In one embodiment, the graphics execution unit 608 can co-issue multipleinstructions, which may each be different instructions. The threadarbiter 622 of the graphics execution unit thread 608 can dispatch theinstructions to one of the send unit 630, branch unit 642, or SIMDFPU(s) 634 for execution. Each execution thread can access 128general-purpose registers within the GRF 624, where each register canstore 32 bytes, accessible as a SIMD 8-element vector of 32-bit dataelements. In one embodiment, each execution unit thread has access to 4Kbytes within the GRF 624, although embodiments are not so limited, andgreater or fewer register resources may be provided in otherembodiments. In one embodiment up to seven threads can executesimultaneously, although the number of threads per execution unit canalso vary according to embodiments. In an embodiment in which seventhreads may access 4 Kbytes, the GRF 624 can store a total of 28 Kbytes.Flexible addressing modes can permit registers to be addressed togetherto build effectively wider registers or to represent strided rectangularblock data structures.

In one embodiment, memory operations, sampler operations, and otherlonger-latency system communications are dispatched via “send”instructions that are executed by the message passing send unit 630. Inone embodiment, branch instructions are dispatched to a dedicated branchunit 632 to facilitate SIMD divergence and eventual convergence.

In one embodiment the graphics execution unit 608 includes one or moreSIMD floating point units (FPU(s)) 634 to perform floating-pointoperations. In one embodiment, the FPU(s) 634 also support integercomputation. In one embodiment the FPU(s) 634 can SIMD execute up to Mnumber of 32-bit floating-point (or integer) operations, or SIMD executeup to 2M 16-bit integer or 16-bit floating-point operations. In oneembodiment, at least one of the FPU(s) provides extended math capabilityto support high-throughput transcendental math functions and doubleprecision 64-bit floating-point. In some embodiments, a set of 8-bitinteger SIMD ALUs 635 are also present, and may be specificallyoptimized to perform operations associated with machine learningcomputations.

In one embodiment, arrays of multiple instances of the graphicsexecution unit 608 can be instantiated in a graphics sub-core grouping(e.g., a sub-slice). For scalability, product architects can chose theexact number of execution units per sub-core grouping. In one embodimentthe execution unit 608 can execute instructions across a plurality ofexecution channels. In a further embodiment, each thread executed on thegraphics execution unit 608 is executed on a different channel.

FIG. 7 is a block diagram illustrating a graphics processor instructionformats 700 according to some embodiments. In one or more embodiment,the graphics processor execution units support an instruction set havinginstructions in multiple formats. The solid lined boxes illustrate thecomponents that are generally included in an execution unit instruction,while the dashed lines include components that are optional or that areonly included in a sub-set of the instructions. In some embodiments,instruction format 700 described and illustrated are macro-instructions,in that they are instructions supplied to the execution unit, as opposedto micro-operations resulting from instruction decode once theinstruction is processed.

In some embodiments, the graphics processor execution units nativelysupport instructions in a 128-bit instruction format 710. A 64-bitcompacted instruction format 730 is available for some instructionsbased on the selected instruction, instruction options, and number ofoperands. The native 128-bit instruction format 710 provides access toall instruction options, while some options and operations arerestricted in the 64-bit format 730. The native instructions availablein the 64-bit format 730 vary by embodiment. In some embodiments, theinstruction is compacted in part using a set of index values in an indexfield 713. The execution unit hardware references a set of compactiontables based on the index values and uses the compaction table outputsto reconstruct a native instruction in the 128-bit instruction format710.

For each format, instruction opcode 712 defines the operation that theexecution unit is to perform. The execution units execute eachinstruction in parallel across the multiple data elements of eachoperand. For example, in response to an add instruction the executionunit performs a simultaneous add operation across each color channelrepresenting a texture element or picture element. By default, theexecution unit performs each instruction across all data channels of theoperands. In some embodiments, instruction control field 714 enablescontrol over certain execution options, such as channels selection(e.g., predication) and data channel order (e.g., swizzle). Forinstructions in the 128-bit instruction format 710 an exec-size field716 limits the number of data channels that will be executed inparallel. In some embodiments, exec-size field 716 is not available foruse in the 64-bit compact instruction format 730.

Some execution unit instructions have up to three operands including twosource operands, src0 720, src1 722, and one destination 718. In someembodiments, the execution units support dual destination instructions,where one of the destinations is implied. Data manipulation instructionscan have a third source operand (e.g., SRC2 724), where the instructionopcode 712 determines the number of source operands. An instruction'slast source operand can be an immediate (e.g., hard-coded) value passedwith the instruction.

In some embodiments, the 128-bit instruction format 710 includes anaccess/address mode field 726 specifying, for example, whether directregister addressing mode or indirect register addressing mode is used.When direct register addressing mode is used, the register address ofone or more operands is directly provided by bits in the instruction.

In some embodiments, the 128-bit instruction format 710 includes anaccess/address mode field 726, which specifies an address mode and/or anaccess mode for the instruction. In one embodiment the access mode isused to define a data access alignment for the instruction. Someembodiments support access modes including a 16-byte aligned access modeand a 1-byte aligned access mode, where the byte alignment of the accessmode determines the access alignment of the instruction operands. Forexample, when in a first mode, the instruction may use byte-alignedaddressing for source and destination operands and when in a secondmode, the instruction may use 16-byte-aligned addressing for all sourceand destination operands.

In one embodiment, the address mode portion of the access/address modefield 726 determines whether the instruction is to use direct orindirect addressing. When direct register addressing mode is used bitsin the instruction directly provide the register address of one or moreoperands. When indirect register addressing mode is used, the registeraddress of one or more operands may be computed based on an addressregister value and an address immediate field in the instruction.

In some embodiments instructions are grouped based on opcode 712bit-fields to simplify Opcode decode 740. For an 8-bit opcode, bits 4,5, and 6 allow the execution unit to determine the type of opcode. Theprecise opcode grouping shown is merely an example. In some embodiments,a move and logic opcode group 742 includes data movement and logicinstructions (e.g., move (mov), compare (cmp)). In some embodiments,move and logic group 742 shares the five most significant bits (MSB),where move (mov) instructions are in the form of 0000xxxxb and logicinstructions are in the form of 0001xxxxb. A flow control instructiongroup 744 (e.g., call, jump (jmp)) includes instructions in the form of0010xxxxb (e.g., 0x20). A miscellaneous instruction group 746 includes amix of instructions, including synchronization instructions (e.g., wait,send) in the form of 0011xxxxb (e.g., 0x30). A parallel math instructiongroup 748 includes component-wise arithmetic instructions (e.g., add,multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel mathgroup 748 performs the arithmetic operations in parallel across datachannels. The vector math group 750 includes arithmetic instructions(e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math groupperforms arithmetic such as dot product calculations on vector operands.

Graphics Pipeline

FIG. 8 is a block diagram of another embodiment of a graphics processor800. Elements of FIG. 8 having the same reference numbers (or names) asthe elements of any other figure herein can operate or function in anymanner similar to that described elsewhere herein, but are not limitedto such.

In some embodiments, graphics processor 800 includes a geometry pipeline820, a media pipeline 830, a display engine 840, thread execution logic850, and a render output pipeline 870. In some embodiments, graphicsprocessor 800 is a graphics processor within a multi-core processingsystem that includes one or more general purpose processing cores. Thegraphics processor is controlled by register writes to one or morecontrol registers (not shown) or via commands issued to graphicsprocessor 800 via a ring interconnect 802. In some embodiments, ringinterconnect 802 couples graphics processor 800 to other processingcomponents, such as other graphics processors or general-purposeprocessors. Commands from ring interconnect 802 are interpreted by acommand streamer 803, which supplies instructions to individualcomponents of the geometry pipeline 820 or the media pipeline 830.

In some embodiments, command streamer 803 directs the operation of avertex fetcher 805 that reads vertex data from memory and executesvertex-processing commands provided by command streamer 803. In someembodiments, vertex fetcher 805 provides vertex data to a vertex shader807, which performs coordinate space transformation and lightingoperations to each vertex. In some embodiments, vertex fetcher 805 andvertex shader 807 execute vertex-processing instructions by dispatchingexecution threads to execution units 852A-852B via a thread dispatcher831.

In some embodiments, execution units 852A-852B are an array of vectorprocessors having an instruction set for performing graphics and mediaoperations. In some embodiments, execution units 852A-852B have anattached L1 cache 851 that is specific for each array or shared betweenthe arrays. The cache can be configured as a data cache, an instructioncache, or a single cache that is partitioned to contain data andinstructions in different partitions.

In some embodiments, geometry pipeline 820 includes tessellationcomponents to perform hardware-accelerated tessellation of 3D objects.In some embodiments, a programmable hull shader 811 configures thetessellation operations. A programmable domain shader 817 providesback-end evaluation of tessellation output. A tessellator 813 operatesat the direction of hull shader 811 and contains special purpose logicto generate a set of detailed geometric objects based on a coarsegeometric model that is provided as input to geometry pipeline 820. Insome embodiments, if tessellation is not used, tessellation components(e.g., hull shader 811, tessellator 813, and domain shader 817) can bebypassed.

In some embodiments, complete geometric objects can be processed by ageometry shader 819 via one or more threads dispatched to executionunits 852A-852B, or can proceed directly to the clipper 829. In someembodiments, the geometry shader operates on entire geometric objects,rather than vertices or patches of vertices as in previous stages of thegraphics pipeline. If the tessellation is disabled the geometry shader819 receives input from the vertex shader 807. In some embodiments,geometry shader 819 is programmable by a geometry shader program toperform geometry tessellation if the tessellation units are disabled.

Before rasterization, a clipper 829 processes vertex data. The clipper829 may be a fixed function clipper or a programmable clipper havingclipping and geometry shader functions. In some embodiments, arasterizer and depth test component 873 in the render output pipeline870 dispatches pixel shaders to convert the geometric objects into perpixel representations. In some embodiments, pixel shader logic isincluded in thread execution logic 850. In some embodiments, anapplication can bypass the rasterizer and depth test component 873 andaccess un-rasterized vertex data via a stream out unit 823.

The graphics processor 800 has an interconnect bus, interconnect fabric,or some other interconnect mechanism that allows data and messagepassing amongst the major components of the processor. In someembodiments, execution units 852A-852B and associated logic units (e.g.,L1 cache 851, sampler 854, texture cache 858, etc.) interconnect via adata port 856 to perform memory access and communicate with renderoutput pipeline components of the processor. In some embodiments,sampler 854, caches 851, 858 and execution units 852A-852B each haveseparate memory access paths. In one embodiment the texture cache 858can also be configured as a sampler cache.

In some embodiments, render output pipeline 870 contains a rasterizerand depth test component 873 that converts vertex-based objects into anassociated pixel-based representation. In some embodiments, therasterizer logic includes a windower/masker unit to perform fixedfunction triangle and line rasterization. An associated render cache 878and depth cache 879 are also available in some embodiments. A pixeloperations component 877 performs pixel-based operations on the data,though in some instances, pixel operations associated with 2D operations(e.g. bit block image transfers with blending) are performed by the 2Dengine 841, or substituted at display time by the display controller 843using overlay display planes. In some embodiments, a shared L3 cache 875is available to all graphics components, allowing the sharing of datawithout the use of main system memory.

In some embodiments, graphics processor media pipeline 830 includes amedia engine 837 and a video front-end 834. In some embodiments, videofront-end 834 receives pipeline commands from the command streamer 803.In some embodiments, media pipeline 830 includes a separate commandstreamer. In some embodiments, video front-end 834 processes mediacommands before sending the command to the media engine 837. In someembodiments, media engine 837 includes thread spawning functionality tospawn threads for dispatch to thread execution logic 850 via threaddispatcher 831.

In some embodiments, graphics processor 800 includes a display engine840. In some embodiments, display engine 840 is external to processor800 and couples with the graphics processor via the ring interconnect802, or some other interconnect bus or fabric. In some embodiments,display engine 840 includes a 2D engine 841 and a display controller843. In some embodiments, display engine 840 contains special purposelogic capable of operating independently of the 3D pipeline. In someembodiments, display controller 843 couples with a display device (notshown), which may be a system integrated display device, as in a laptopcomputer, or an external display device attached via a display deviceconnector.

In some embodiments, the geometry pipeline 820 and media pipeline 830are configurable to perform operations based on multiple graphics andmedia programming interfaces and are not specific to any one applicationprogramming interface (API). In some embodiments, driver software forthe graphics processor translates API calls that are specific to aparticular graphics or media library into commands that can be processedby the graphics processor. In some embodiments, support is provided forthe Open Graphics Library (OpenGL), Open Computing Language (OpenCL),and/or Vulkan graphics and compute API, all from the Khronos Group. Insome embodiments, support may also be provided for the Direct3D libraryfrom the Microsoft Corporation. In some embodiments, a combination ofthese libraries may be supported. Support may also be provided for theOpen Source Computer Vision Library (OpenCV). A future API with acompatible 3D pipeline would also be supported if a mapping can be madefrom the pipeline of the future API to the pipeline of the graphicsprocessor.

Graphics Pipeline Programming

FIG. 9A is a block diagram illustrating a graphics processor commandformat 900 according to some embodiments. FIG. 9B is a block diagramillustrating a graphics processor command sequence 910 according to anembodiment. The solid lined boxes in FIG. 9A illustrate the componentsthat are generally included in a graphics command while the dashed linesinclude components that are optional or that are only included in asub-set of the graphics commands. The exemplary graphics processorcommand format 900 of FIG. 9A includes data fields to identify a client902, a command operation code (opcode) 904, and data 906 for thecommand. A sub-opcode 905 and a command size 908 are also included insome commands.

In some embodiments, client 902 specifies the client unit of thegraphics device that processes the command data. In some embodiments, agraphics processor command parser examines the client field of eachcommand to condition the further processing of the command and route thecommand data to the appropriate client unit. In some embodiments, thegraphics processor client units include a memory interface unit, arender unit, a 2D unit, a 3D unit, and a media unit. Each client unithas a corresponding processing pipeline that processes the commands.Once the command is received by the client unit, the client unit readsthe opcode 904 and, if present, sub-opcode 905 to determine theoperation to perform. The client unit performs the command usinginformation in data field 906. For some commands an explicit commandsize 908 is expected to specify the size of the command. In someembodiments, the command parser automatically determines the size of atleast some of the commands based on the command opcode. In someembodiments commands are aligned via multiples of a double word.

The flow diagram in FIG. 9B illustrates an exemplary graphics processorcommand sequence 910. In some embodiments, software or firmware of adata processing system that features an embodiment of a graphicsprocessor uses a version of the command sequence shown to set up,execute, and terminate a set of graphics operations. A sample commandsequence is shown and described for purposes of example only asembodiments are not limited to these specific commands or to thiscommand sequence. Moreover, the commands may be issued as batch ofcommands in a command sequence, such that the graphics processor willprocess the sequence of commands in at least partially concurrence.

In some embodiments, the graphics processor command sequence 910 maybegin with a pipeline flush command 912 to cause any active graphicspipeline to complete the currently pending commands for the pipeline. Insome embodiments, the 3D pipeline 922 and the media pipeline 924 do notoperate concurrently. The pipeline flush is performed to cause theactive graphics pipeline to complete any pending commands. In responseto a pipeline flush, the command parser for the graphics processor willpause command processing until the active drawing engines completepending operations and the relevant read caches are invalidated.Optionally, any data in the render cache that is marked ‘dirty’ can beflushed to memory. In some embodiments, pipeline flush command 912 canbe used for pipeline synchronization or before placing the graphicsprocessor into a low power state.

In some embodiments, a pipeline select command 913 is used when acommand sequence requires the graphics processor to explicitly switchbetween pipelines. In some embodiments, a pipeline select command 913 isrequired only once within an execution context before issuing pipelinecommands unless the context is to issue commands for both pipelines. Insome embodiments, a pipeline flush command 912 is required immediatelybefore a pipeline switch via the pipeline select command 913.

In some embodiments, a pipeline control command 914 configures agraphics pipeline for operation and is used to program the 3D pipeline922 and the media pipeline 924. In some embodiments, pipeline controlcommand 914 configures the pipeline state for the active pipeline. Inone embodiment, the pipeline control command 914 is used for pipelinesynchronization and to clear data from one or more cache memories withinthe active pipeline before processing a batch of commands.

In some embodiments, return buffer state commands 916 are used toconfigure a set of return buffers for the respective pipelines to writedata. Some pipeline operations require the allocation, selection, orconfiguration of one or more return buffers into which the operationswrite intermediate data during processing. In some embodiments, thegraphics processor also uses one or more return buffers to store outputdata and to perform cross thread communication. In some embodiments, thereturn buffer state 916 includes selecting the size and number of returnbuffers to use for a set of pipeline operations.

The remaining commands in the command sequence differ based on theactive pipeline for operations. Based on a pipeline determination 920,the command sequence is tailored to the 3D pipeline 922 beginning withthe 3D pipeline state 930 or the media pipeline 924 beginning at themedia pipeline state 940.

The commands to configure the 3D pipeline state 930 include 3D statesetting commands for vertex buffer state, vertex element state, constantcolor state, depth buffer state, and other state variables that are tobe configured before 3D primitive commands are processed. The values ofthese commands are determined at least in part based on the particular3D API in use. In some embodiments, 3D pipeline state 930 commands arealso able to selectively disable or bypass certain pipeline elements ifthose elements will not be used.

In some embodiments, 3D primitive 932 command is used to submit 3Dprimitives to be processed by the 3D pipeline. Commands and associatedparameters that are passed to the graphics processor via the 3Dprimitive 932 command are forwarded to the vertex fetch function in thegraphics pipeline. The vertex fetch function uses the 3D primitive 932command data to generate vertex data structures. The vertex datastructures are stored in one or more return buffers. In someembodiments, 3D primitive 932 command is used to perform vertexoperations on 3D primitives via vertex shaders. To process vertexshaders, 3D pipeline 922 dispatches shader execution threads to graphicsprocessor execution units.

In some embodiments, 3D pipeline 922 is triggered via an execute 934command or event. In some embodiments, a register write triggers commandexecution. In some embodiments execution is triggered via a ‘go’ or‘kick’ command in the command sequence. In one embodiment, commandexecution is triggered using a pipeline synchronization command to flushthe command sequence through the graphics pipeline. The 3D pipeline willperform geometry processing for the 3D primitives. Once operations arecomplete, the resulting geometric objects are rasterized and the pixelengine colors the resulting pixels. Additional commands to control pixelshading and pixel back end operations may also be included for thoseoperations.

In some embodiments, the graphics processor command sequence 910 followsthe media pipeline 924 path when performing media operations. Ingeneral, the specific use and manner of programming for the mediapipeline 924 depends on the media or compute operations to be performed.Specific media decode operations may be offloaded to the media pipelineduring media decode. In some embodiments, the media pipeline can also bebypassed and media decode can be performed in whole or in part usingresources provided by one or more general purpose processing cores. Inone embodiment, the media pipeline also includes elements forgeneral-purpose graphics processor unit (GPGPU) operations, where thegraphics processor is used to perform SIMD vector operations usingcomputational shader programs that are not explicitly related to therendering of graphics primitives.

In some embodiments, media pipeline 924 is configured in a similarmanner as the 3D pipeline 922. A set of commands to configure the mediapipeline state 940 are dispatched or placed into a command queue beforethe media object commands 942. In some embodiments, commands for themedia pipeline state 940 include data to configure the media pipelineelements that will be used to process the media objects. This includesdata to configure the video decode and video encode logic within themedia pipeline, such as encode or decode format. In some embodiments,commands for the media pipeline state 940 also support the use of one ormore pointers to “indirect” state elements that contain a batch of statesettings.

In some embodiments, media object commands 942 supply pointers to mediaobjects for processing by the media pipeline. The media objects includememory buffers containing video data to be processed. In someembodiments, all media pipeline states must be valid before issuing amedia object command 942. Once the pipeline state is configured andmedia object commands 942 are queued, the media pipeline 924 istriggered via an execute command 944 or an equivalent execute event(e.g., register write). Output from media pipeline 924 may then be postprocessed by operations provided by the 3D pipeline 922 or the mediapipeline 924. In some embodiments, GPGPU operations are configured andexecuted in a similar manner as media operations.

Graphics Software Architecture

FIG. 10 illustrates exemplary graphics software architecture for a dataprocessing system 1000 according to some embodiments. In someembodiments, software architecture includes a 3D graphics application1010, an operating system 1020, and at least one processor 1030. In someembodiments, processor 1030 includes a graphics processor 1032 and oneor more general-purpose processor core(s) 1034. The graphics application1010 and operating system 1020 each execute in the system memory 1050 ofthe data processing system.

In some embodiments, 3D graphics application 1010 contains one or moreshader programs including shader instructions 1012. The shader languageinstructions may be in a high-level shader language, such as the HighLevel Shader Language (HLSL) or the OpenGL Shader Language (GLSL). Theapplication also includes executable instructions 1014 in a machinelanguage suitable for execution by the general-purpose processor core1034. The application also includes graphics objects 1016 defined byvertex data.

In some embodiments, operating system 1020 is a Microsoft® Windows®operating system from the Microsoft Corporation, a proprietary UNIX-likeoperating system, or an open source UNIX-like operating system using avariant of the Linux kernel. The operating system 1020 can support agraphics API 1022 such as the Direct3D API, the OpenGL API, or theVulkan API. When the Direct3D API is in use, the operating system 1020uses a front-end shader compiler 1024 to compile any shader instructions1012 in HLSL into a lower-level shader language. The compilation may bea just-in-time (JIT) compilation or the application can perform shaderpre-compilation. In some embodiments, high-level shaders are compiledinto low-level shaders during the compilation of the 3D graphicsapplication 1010. In some embodiments, the shader instructions 1012 areprovided in an intermediate form, such as a version of the StandardPortable Intermediate Representation (SPIR) used by the Vulkan API.

In some embodiments, user mode graphics driver 1026 contains a back-endshader compiler 1027 to convert the shader instructions 1012 into ahardware specific representation. When the OpenGL API is in use, shaderinstructions 1012 in the GLSL high-level language are passed to a usermode graphics driver 1026 for compilation. In some embodiments, usermode graphics driver 1026 uses operating system kernel mode functions1028 to communicate with a kernel mode graphics driver 1029. In someembodiments, kernel mode graphics driver 1029 communicates with graphicsprocessor 1032 to dispatch commands and instructions.

IP Core Implementations

One or more aspects of at least one embodiment may be implemented byrepresentative code stored on a machine-readable medium which representsand/or defines logic within an integrated circuit such as a processor.For example, the machine-readable medium may include instructions whichrepresent various logic within the processor. When read by a machine,the instructions may cause the machine to fabricate the logic to performthe techniques described herein. Such representations, known as “IPcores,” are reusable units of logic for an integrated circuit that maybe stored on a tangible, machine-readable medium as a hardware modelthat describes the structure of the integrated circuit. The hardwaremodel may be supplied to various customers or manufacturing facilities,which load the hardware model on fabrication machines that manufacturethe integrated circuit. The integrated circuit may be fabricated suchthat the circuit performs operations described in association with anyof the embodiments described herein.

FIG. 11 is a block diagram illustrating an IP core development system1100 that may be used to manufacture an integrated circuit to performoperations according to an embodiment. The IP core development system1100 may be used to generate modular, re-usable designs that can beincorporated into a larger design or used to construct an entireintegrated circuit (e.g., an SOC integrated circuit). A design facility1130 can generate a software simulation 1110 of an IP core design in ahigh level programming language (e.g., C/C++). The software simulation1110 can be used to design, test, and verify the behavior of the IP coreusing a simulation model 1112. The simulation model 1112 may includefunctional, behavioral, and/or timing simulations. A register transferlevel (RTL) design 1115 can then be created or synthesized from thesimulation model 1112. The RTL design 1115 is an abstraction of thebehavior of the integrated circuit that models the flow of digitalsignals between hardware registers, including the associated logicperformed using the modeled digital signals. In addition to an RTLdesign 1115, lower-level designs at the logic level or transistor levelmay also be created, designed, or synthesized. Thus, the particulardetails of the initial design and simulation may vary.

The RTL design 1115 or equivalent may be further synthesized by thedesign facility into a hardware model 1120, which may be in a hardwaredescription language (HDL), or some other representation of physicaldesign data. The HDL may be further simulated or tested to verify the IPcore design. The IP core design can be stored for delivery to a 3^(rd)party fabrication facility 1165 using non-volatile memory 1140 (e.g.,hard disk, flash memory, or any non-volatile storage medium).Alternatively, the IP core design may be transmitted (e.g., via theInternet) over a wired connection 1150 or wireless connection 1160. Thefabrication facility 1165 may then fabricate an integrated circuit thatis based at least in part on the IP core design. The fabricatedintegrated circuit can be configured to perform operations in accordancewith at least one embodiment described herein.

Exemplary System on a Chip Integrated Circuit

FIGS. 12-14 illustrated exemplary integrated circuits and associatedgraphics processors that may be fabricated using one or more IP cores,according to various embodiments described herein. In addition to whatis illustrated, other logic and circuits may be included, includingadditional graphics processors/cores, peripheral interface controllers,or general purpose processor cores.

FIG. 12 is a block diagram illustrating an exemplary system on a chipintegrated circuit 1200 that may be fabricated using one or more IPcores, according to an embodiment. Exemplary integrated circuit 1200includes one or more application processor(s) 1205 (e.g., CPUs), atleast one graphics processor 1210, and may additionally include an imageprocessor 1215 and/or a video processor 1220, any of which may be amodular IP core from the same or multiple different design facilities.Integrated circuit 1200 includes peripheral or bus logic including a USBcontroller 1225, UART controller 1230, an SPI/SDIO controller 1235, andan I²S/I²C controller 1240. Additionally, the integrated circuit caninclude a display device 1245 coupled to one or more of ahigh-definition multimedia interface (HDMI) controller 1250 and a mobileindustry processor interface (MIPI) display interface 1255. Storage maybe provided by a flash memory subsystem 1260 including flash memory anda flash memory controller. Memory interface may be provided via a memorycontroller 1265 for access to SDRAM or SRAM memory devices. Someintegrated circuits additionally include an embedded security engine1270.

FIGS. 13A-13B are block diagrams illustrating exemplary graphicsprocessors for use within an SoC, according to embodiments describedherein. FIG. 13A illustrates an exemplary graphics processor 1310 of asystem on a chip integrated circuit that may be fabricated using one ormore IP cores, according to an embodiment. FIG. 13B illustrates anadditional exemplary graphics processor 1340 of a system on a chipintegrated circuit that may be fabricated using one or more IP cores,according to an embodiment. Graphics processor 1310 of FIG. 13A is anexample of a low power graphics processor core. Graphics processor 1340of FIG. 13B is an example of a higher performance graphics processorcore. Each of the graphics processors 1310, 1340 can be variants of thegraphics processor 1210 of FIG. 12.

As shown in FIG. 13A, graphics processor 1310 includes a vertexprocessor 1305 and one or more fragment processor(s) 1315A-1315N (e.g.,1315A, 1315B, 1315C, 1315D, through 1315N-1, and 1315N). Graphicsprocessor 1310 can execute different shader programs via separate logic,such that the vertex processor 1305 is optimized to execute operationsfor vertex shader programs, while the one or more fragment processor(s)1315A-1315N execute fragment (e.g., pixel) shading operations forfragment or pixel shader programs. The vertex processor 1305 performsthe vertex processing stage of the 3D graphics pipeline and generatesprimitives and vertex data. The fragment processor(s) 1315A-1315N usethe primitive and vertex data generated by the vertex processor 1305 toproduce a framebuffer that is displayed on a display device. In oneembodiment, the fragment processor(s) 1315A-1315N are optimized toexecute fragment shader programs as provided for in the OpenGL API,which may be used to perform similar operations as a pixel shaderprogram as provided for in the Direct 3D API.

Graphics processor 1310 additionally includes one or more memorymanagement units (MMUs) 1320A-1320B, cache(s) 1325A-1325B, and circuitinterconnect(s) 1330A-1330B. The one or more MMU(s) 1320A-1320B providefor virtual to physical address mapping for the graphics processor 1310,including for the vertex processor 1305 and/or fragment processor(s)1315A-1315N, which may reference vertex or image/texture data stored inmemory, in addition to vertex or image/texture data stored in the one ormore cache(s) 1325A-1325B. In one embodiment the one or more MMU(s)1320A-1320B may be synchronized with other MMUs within the system,including one or more MMUs associated with the one or more applicationprocessor(s) 1205, image processor 1215, and/or video processor 1220 ofFIG. 12, such that each processor 1205-1220 can participate in a sharedor unified virtual memory system. The one or more circuitinterconnect(s) 1330A-1330B enable graphics processor 1310 to interfacewith other IP cores within the SoC, either via an internal bus of theSoC or via a direct connection, according to embodiments.

As shown FIG. 13B, graphics processor 1340 includes the one or moreMMU(s) 1320A-1320B, caches 1325A-1325B, and circuit interconnects1330A-1330B of the graphics processor 1310 of FIG. 13A. Graphicsprocessor 1340 includes one or more shader core(s) 1355A-1355N (e.g.,1455A, 1355B, 1355C, 1355D, 1355E, 1355F, through 1355N-1, and 1355N),which provides for a unified shader core architecture in which a singlecore or type or core can execute all types of programmable shader code,including shader program code to implement vertex shaders, fragmentshaders, and/or compute shaders. The exact number of shader corespresent can vary among embodiments and implementations. Additionally,graphics processor 1340 includes an inter-core task manager 1345, whichacts as a thread dispatcher to dispatch execution threads to one or moreshader cores 1355A-1355N and a tiling unit 1358 to accelerate tilingoperations for tile-based rendering, in which rendering operations for ascene are subdivided in image space, for example to exploit localspatial coherence within a scene or to optimize use of internal caches.

FIG. 14 illustrates additional exemplary graphics processor logicaccording to embodiments described herein. One embodiment provides agraphics core 1400 that may be included within the graphics processor1210 of FIG. 12, and may be a unified shader core 1355A-1355N as in FIG.13B. The graphics core 1400 includes a shared instruction cache 1402, atexture unit 1418, and a cache/shared memory 1420 that are common to theexecution resources within the graphics core 1400. The graphics core1400 can include multiple slices 1401A-1401N or partition for each core,and a graphics processor can include multiple instances of the graphicscore 1400. The slices 1401A-1401N can include support logic including alocal instruction cache 1404A-1404N, a thread scheduler 1406A-1406N, athread dispatcher 1408A-1408N, and a set of registers 1410A. To performlogic operations, the slices 1401A-1401N can include a set of additionalfunction units (AFUs 1412A-1412N), floating-point units (FPU1414A-1414N), integer arithmetic logic units (ALUs 1416-1416N), addresscomputational units (ACU 1413A-1413N), double-precision floating-pointunits (DPFPU 1415A-1415N), and matrix processing units (MPU1417A-1417N).

Some of the computational units operate at a specific precision. Forexample, the FPUs 1414A-1414N can perform single-precision (32-bit) andhalf-precision (16-bit) floating point operations, while the DPFPUs1415A-1415N perform double precision (64-bit) floating point operations.The ALUs 1416A-1416N can perform variable precision integer operationsat 8-bit, 16-bit, and 32-bit precision, and can be configured for mixedprecision operations. The MPUs 1417A-1417N can also be configured formixed precision matrix operations, including half-precision floatingpoint and 8-bit integer operations. The MPUs 1417-1417N can perform avariety of matrix operations to accelerate machine learning applicationframeworks, including enabling support for accelerated general matrix tomatrix multiplication (GEMM). The AFUs 1412A-1412N can performadditional logic operations not supported by the floating-point orinteger units, including trigonometric operations (e.g., Sine, Cosine,etc.).

Winograd Convolution Accelerator Architecture

Embodiments described herein provide a scalable hardware architecture toenable a deep learning convolution accelerator having logic to performgeneralized Winograd convolution for multiple kernel sizes and kernelstrides without requiring hardware support for multiple Winogradtransforms. The deep learning convolution accelerator supports allkernel sizes by using lower order 1-D filter Winograd F(4,3) method thatsupports convolutions with stride greater than 1. In one embodiment thecost of Winograd transform for higher order kernels is minimized byreusing the transforms of the lower order F(4,3). In general, thearchitecture provided herein addresses Winograd transform based CNNacceleration on a multi-dimensional SIMD machine. The architectureimproves convolution performance while improving the compute per byte.Winograd transform based CNN accelerators can provide a ˜2× improvementover other accelerators. Winograd enables faster convolution by reducingthe number of multiplications within compute operations by transformingthe inputs and kernels (e.g. filters) into a form that enables higherperformance for given hardware resources. The Winograd transforms areperformed on the fly and broadcasted to parallel compute logic (e.g.,SIMD, SIMT, etc.) without increasing the bandwidth requirements for thehardware. Additionally, the reduced number of compute operations alsoresults in an increase in performance per watt.

Deep learning neural networks are compute intensive and large networkscan be performance limited. Embodiments described herein provide customacceleration logic to accelerate the compute intensive workloadsassociated with deep learning neural networks, such as convolutionalneural networks (CNNs). In CNNs, each layer performs 3D convolution onan input feature map, where each layer has different Kernel size andStride requirements. In deep learning inference applications, it isimportant to achieve highest performance/watt and or performance/area.Direct convolution can be used to perform the above computations, butthere exist a new class of fast algorithms for convolutional neuralnetworks based on the minimal filtering algorithms pioneered byWinograd. However, the Winograd method requires different computationalstructure for different kernel size/stride, which limits the efficientuse of Winograd transforms in hardware accelerators for neural networks.

Embodiments descried herein provide a unified hardware architecture thatis based on F(4,3) Winograd Kernel convolution and derive higher orderconvolutions based on this base kernel. The derivation is performed inan optimized manner to achieve maximum performance per watt. Embodimentsdescribed herein make use of inline Kernel and Input data transformswithout causing bandwidth increase and requiring minimal hardwarecomplexity. The proposed hardware accelerator is configurable andscalable for efficient calculations of 3D convolutions using Winograd.

FIGS. 15A-15B illustrate Native and Winograd based 3D convolutions. FIG.15A illustrates a 3D convolution operation 1500 for a convolutionalneural network. FIG. 15B illustrates details of Winograd basedconvolution 1510 and native convolution 1520. The 3D convolutionoperation 1500 illustrated in FIG. 15A are key to convolution neuralnetworks, which are suited for computer vision and speech accelerationapplications. In 3D convolution, each input feature map (IFM) in a setof input feature maps 1502 (IFM1 through IFM N) is convolved 1504 with acorresponding convolution filter (K1) (e.g., K1, IFM1 through K1, IFMn).The partial results 1506 are summed to create a final output feature map(OFM) 1508. Processing operations for the convolution neural networkrequires many such 3D convolutions to be performed on the same IFMs toproduce different OFMs.

As illustrated in FIG. 15B, embodiments described herein providehardware accelerate logic that makes use of Winograd based convolution1510 to enable CNN processing with reduced multiplications relative tonative convolution 1520. In one embodiment, a Winograd transform is usedto compute 1D convolutions for four pixels. This convolution can berepeated over the whole input feature map to compute the full outputfeature map. For example, a 1×3 kernel 1511 and a 1×6 input feature mappatch can be transformed via a weight transform unit 1513 and an inputtransform unit 1514. The transformed 1×6 matrices can be processed viaan element wise multiplication unit 1515 can perform the convolution.The convolution can be performed using six multiplications to generate a1×6 intermediate output matrix. An output transform unit 1516 transformsthe 1×6 intermediate output matrix into a 1×4 output 1518. The Winogradbased convolution 1510 enables a reduced number of multiplicationsrelative to native convolution 1520. To transform the 1×3 kernel 1511and 1×6 IMF patch 1512 using native convolution 1520 utilizes a nativeconvolution unit 1525, which requires 12 multiplications to generate thesame 1×4 output matrix 1518. The acceleration architecture provided byembodiments described herein minimizes the cost of transformssignificantly by reusing the input transform across all output featuremaps, computing the transform in parallel. In one embodiment thetransformed weights are stored in local memory to reuse across theentire output feature map. Different filter sizes can also be mapped tothe same weight transform, which is a onetime operation for each filter.The broadcasting of transformed inputs amortizes the cost of thetransform with negligible broadcast costs.

Winograd Support for Generic Kernel Sizes

FIG. 16 illustrates an architecture 1600 for 2D/3D convolutions based onthe F[4,3] convolution. The illustrated architecture 1600 breaks a 2Dconvolution filter into multiple 1-D kernels and performs Winograd basedconvolution to produce 2-D convolution output. The same transform isapplied on multiple IFMs to produce a 3-D convolution output. In oneembodiment, the illustrated architecture 1600 is implemented in part viahardware logic configured as a Winograd compute block 1640. The Winogradcompute block 1640 performs a convolution operation 1615 using a [1×6]tensor 1612 from an input feature map 1610 and a [1×3] tensor 1622 froma convolution kernel 1620 to generate a [1×4] tensor 1632 that is aportion of an output feature map 1630.

For example, to perform 1-D convolution of size 1×5 using 1×3 Kernel,the following operations can be performed. A given 1×5 kernel K can bedefined, where K=[1 2 3 4 5]. This 1×5 Kernel can be decomposed tosub-kernels K₀ and K₁ of size 1×3, where K₀=[1 2 3] and K₁=[4 5 0].Compute logic, using K₀ and K₁, can perform Winograd based convolutionwith a corresponding patch of the IFM. The results can be combined toobtain a final result of kernel size [1×5]. The Winograd convolution canbe performed using 12 multiplications, compared to 20 multiplicationsfor native convolution, resulting in a 1.67× gain compared to nativeconvolution. The process is repeated over 5 rows of the kernel to obtainthe convolution result of size [5×5] filter. This approach is genericand can be applied to filters of any size. The proposed hardwarearchitecture handles the decomposition of kernel and computing higherorder kernels in multiple loops.

FIG. 17 illustrates logic 1700 to generalize F(4,3) Winograd convolutionto higher order kernels. The logic 1700 can be used to enable Winogradconvolution for kernels of general size using a decomposition intomultiple [1×3] kernels. In one embodiment the illustrated logic 1700 isimplemented via hardware processing elements configured to performWinograd convolution. The logic 1700 performs a first operation 1702 todetermine values N and M. N specifies the number of Winograd operationpasses to be performed for each row and M specifies the number of rowsof operations to perform. N is computed by ceiling (Kernel_Size/3) and Mis determined by the (Kernel_Size). For an exemplary Kernel_Size of 5,N=2 and M=5. The logic 1700 also performs a second operation 1704 tomaintain values defining the next input data row (X) and next kernel row(K). Before performing a set of operations for a row, the logic 1700performs an operation 1705 to determine if N equals zero. If N is notequal to zero, an operation 1706 is performed to load a 1D input tensor(e.g., X_(n)=X(1:6)) and Kernel data (K_(n)=X(1:3)) for a processingelement operation. Operation 1710 provides the input and kernel tensordata to a Winograd Processing Element (WPE), which performs a Winogradtransform on the input and weight tensor, an element-wise multiplicationbetween the transformed inputs and weights, and a vector accumulateoperation that adds the output of the multiplication (e.g., a partialoutput feature map) to a tensor value within an accumulator register, asshown by the illustrated operations, {Wx=B^(T)X_(n); Wk=Gk_(n);Y_(n)=Y_(n_Prev)+Wx*Wk; Y_(n_Prev)=Y_(n)}. Wx and Wk are Winogradtransformations of the input and kernel tensor data and Wx*Wk is anelementwise multiplication of the Winograd transformed tensors.Y_(n_Prev) represents the sum of the previous partial output featuremaps. B^(T) and G are F(4,3) Winograd transform matrices for input andKernel data that are defined as:

$B^{T} = \begin{bmatrix}4 & 0 & {- 5} & 0 & 1 & 0 \\0 & {- 4} & {- 4} & 1 & 1 & 0 \\0 & 4 & {- 4} & {- 1} & 1 & 0 \\0 & {- 2} & {- 1} & 2 & 1 & 0 \\0 & {- 2} & {- 1} & {- 2} & 1 & 0 \\0 & 4 & 0 & {- 5} & 0 & 1\end{bmatrix}$ $G = \begin{bmatrix}{1/4} & 0 & 0 \\{{- 1}/6} & {{- 1}/6} & {{- 1}/6} \\{{- 1}/6} & {1/6} & {{- 1}/6} \\{1/24} & {1/12} & {1/6} \\{1/24} & {{- 1}/12} & {1/6} \\0 & 0 & 1\end{bmatrix}$

The logic 1700 then performs operation 1712 to select the next set ofinput and weight data within a row {N=N−1;X=X<<3;K=K<<3}. The logic 1700returns to operation 1705 to determine if additional passes for a roware required. Once the passes for a row are complete (e.g., N==0), thelogic 1700 can move to the next row (e.g., M=M−1 at operation 1708).Until all rows are processed (e.g., M==0 at operation 1709), the logicreturns to operation 1704. Once the logic 1700 completes processing foreach row, as determined via operation 1709, the logic 1700 can performan inverse transform operation 1714 in which an inverse Winogradtransform is performed on a summed output feature map Y. (e.g.,Y_(Out)=A^(T)Y_(n)), where A^(T) is an inverse Winograd transform for anoutput feature map, defined as:

$A^{T} = \begin{bmatrix}1 & 1 & 1 & 1 & 1 & 0 \\0 & 1 & {- 1} & 2 & {- 2} & 0 \\0 & 1 & 1 & 4 & 4 & 0 \\0 & 1 & {- 1} & 8 & {- 8} & 1\end{bmatrix}$

Multi Stride Convolution

Winograd transform brings the efficiency in compute by reducing themultiplication required to compute adjacent pixels. For convolutionallayers which work on stride >1, conventional solutions would require theWinograd transform to be modified. For example, convolution with stride2 would perform the convolution operation for alternate pixels. In orderto support strides greater than one using a conventional Winogradtransform, inputs data is modified using steering write logic, whichmodifies the input data when writing the data to internal memory of theaccelerator.

FIG. 18 illustrates an exemplary logic and data layout 1800 to enablemulti-stride convolution, according to an embodiment. The exemplarylogic and data layout 1800 is configured for kernel size of five and akernel stride of two. In one embodiment, a steering logic block (e.g.,steering write logic 1806) is provided that hides the alternate pixelsfrom Winograd transform. A 1×5 kernel 1802 having elements {k1, k2, k3,k4, k5} can be decomposed into two 1×3 kernels based on an exemplarykernel stride of two, where a first decomposed kernel 1808A includeselements {k1, K3, and K5}, while a second decomposed kernel 1808Bincludes elements {k2, k4, 0}. A patch of input data 1804 that is storedcontiguously in memory can be written out to a buffer within Winogradcompute logic via steering write logic 1806. The steering write logiccan write the input data such that data of stride 2 is storedcontiguously within the buffer. For example, a 1×12 input patch havingelements {I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12} can bewritten out to a buffer, such that a first input data tensor 1812Aincludes elements {I1, I3, I5, I7, I9, I11} and a second input datatensor 1812 includes elements {I2, I4, I6, I8, I10, I12}. A Winogradcompute unit 1810 can then perform an F(4,3) Winograd convolutionbetween the respective 1×3 kernels 1808A-1808B and 1×6 input datatensors 1812A-1812B, the partial outputs being summed to create a finaloutput 1814. The illustrated technique can be modified as necessary toenable multi-stride convolution of various strides, as control logic,such as the steering write logic 1806 can be configured accordingly forvarious strides greater than one.

High Level Architecture:

FIG. 19 is a block diagram of a Winograd acceleration architecture 1900according to embodiments described herein. The illustrated accelerationarchitecture 1900 has a parameterizable number of processing tiles1910A-1910M (e.g., Tile-0 through Tile-M), each tile having an array ofWinograd compute blocks 1914A-1914N (WINO-Block-1 through WINO-Block-N)to perform convolution operations using Winograd transforms. In oneembodiment the Winograd acceleration logic 1900 includes a computeinterface 1902, which can be one of any number of high-performancecompute interfaces, including network-based interfaces. The computeinterface 1902 sends and receives commands and data to a local DMA unit1901. The local DMA unit 1901 is a data fetch engine that includes avariety of memory access and transmission logic units capable ofperforming load and store operations to and from the various memoryunits within the Winograd acceleration architecture 1900.

The Winograd acceleration architecture 1900 additionally includes aninput write controller 1903 and a kernel write controller 1926, whicheach include steering logic, such as the steering write logic 1806 ofFIG. 18, to enable support for multi-stride convolution. The kernelwrite controller 1926 is also configured to distribute specific kerneldata to specific tiles 1910A-1910M. A set of IP registers 1924 includesaccelerator configuration registers to provide topology information tothe Winograd acceleration architecture 1900. Provided topologyinformation incudes kernel and input patch size, kernel stride, numberof input and output feature maps, and other information used toconfigure convolution operations within the Winograd accelerationarchitecture 1900. In one embodiment, a separate control interface isprovided to configure the IP registers 1924. The IP registers 1924 canbe configured on a layer-by-layer basis, such that each CNN layer can beconfigured differently. In one embodiment, the layer-by-layer topologyof an entire CNN model can be pre-configured within the IP registers1924 to enable streamlined processing of the CNN.

One embodiment additionally includes a Winograd controller 1922, whichis a core controller that controls compute loops and data access to andfrom local memories (e.g., input local memory 1904) based on topologyinformation provided to the IP registers 1924. In one embodiment theWinograd controller 1922 is a microcontroller that controls the controlflow for the operations performed by the Winograd compute blocks1914A-1914N within each tile 1910A-1910M. Control flow control performby the Winograd controller includes determining the manner and order inwhich the partial and final output feature maps are computed. TheWinograd controller 1922, in one embodiment, manages control flow byissuing commands and instructions to the Winograd compute blocks1914A-1914N within each tile 1910A-1910M. In one embodiment the Winogradcontroller 1922 can perform fine-grained control of the Winograd computeblocks 1914A-1914N, including issuing specific multiply and accumulateinstructions for various phases of the Winograd convolution. TheWinograd controller 1922 can also sequence and issue a series of complexlogic operations to enable multi-stride and multi-sized kernelconvolution, as described herein, using a single Winograd transform(e.g., the F(4,3) Winograd transform), enabling the Winograd computearchitecture 1900 to support multiple kernel sizes and kernel strideswithout requiring hardware logic to support multiple different types oftransforms. Although the architecture described herein is configured forthe F(4,3) Winograd transform, other embodiments can implement similartechniques using hardware designed for other Winograd transforms{F(m,r)}, where such hardware computes m outputs using an r-tap finiteimpulse response (FIR) filter defined at least in part via a 1×r kernel.

The Winograd compute architecture 1900 includes various internalmemories, such as input local memory 1904, output local memory 1916, andKernel local memory 1912. The input local memory 1904 is used to storethe minimum input data required to start the compute. Data stored in theinput local memory 1904 can be reused across all processing tiles1910A-1910M. Data from the input local memory 1904 can be transformed byan input transform unit 1905 when provided to the various processingtiles 1910A-1910M. Additional details on input transform and the inputtransform unit 1905 is described with respect to FIG. 20.

The output local memory 1916 is included within each processing tile1910A-1910M and stores partially computed output data. The kernel localmemory 1912 stores kernel data to use in output feature map compute. Thekernel local memory 1912 is included within each processing tile1910A-1910M and stores transformed kernel data output by a weighttransform unit 1911. The transformed weight data can be re-used by eachWinograd compute block 1914A-1914N within a single tile, with each tile1910A-1910M including a separate weight transform unit 1911. The weighttransform cost is paid per tile, as each tile computes a differentoutput feature map, where each output feature map is associated with adifferent kernel. The weight transform is done before writing to kernellocal memory 1912, enabling reuse across the entire output feature mapcompute, enabling a reduction in operational power for the Winogradacceleration architecture 1900. Additional optimizations to the weighttransform unit 1911 are described with respect to FIG. 22.

Data stored in input local memory 1904 can be re-used across allprocessing tiles 1910A-1910M. Kernel transformed data is re-used acrossall Winograd compute blocks 1914A-1914N within each tile. In oneembodiment, each of the Winograd compute blocks 1914A-1914N includemultiple multiply accumulate compute units to perform multipleelementwise multiplication and accumulate operations to generate partialresults for all input feature maps. Additional information on theWinograd compute blocks 1914A-1914N is provided with respect to FIG. 21.

In one embodiment Intermediate data is stored in output local memory1916 before transformation by an output transform unit 1918. The outputtransform unit 1918 performs output transforms for all tiles1910A-1910M, avoiding the need to perform an output transform withineach tile. In one embodiment, the output transform unit 1918 can performan output transform (e.g., inverse Winograd transform) for a 1×6 outputtensor to generate a 1×4 output tensor. The output transform can beperformed in parallel for one or more of the tiles 1910A-1910M. Outputwrite is controlled by an output write control unit 1920, which readsoutput data and writes the output data to external memory via the localDMA unit 1901. In one embodiment the output transform unit 1918 canautomatically perform an inverse Winograd transform for output featuremaps that are read from the output local memory 1916 by the output writecontrol 1920. The output write control unit 1920 reads the data from theoutput local memory 1916 in each tile 1910A-1910M and arranges the datain the proper write format from use by the local DMA unit 1901. In oneembodiment the output write control 1920 serializes output from eachtile 1910A-1910M to reduce the amount of memory bandwidth consumed bythe output write. While output write is serialized in such embodiment,compute operations within each tile 1910A-1910M is performed inparallel. During the draining of output data from local memory, anyrequired bias additions are performed if required.

FIG. 20 illustrates input transform, according to an embodiment. TheInput transform, in one embodiment, is performed by an input transformunit, such as the input transform unit 1905 in FIG. 19. The data of theinput feature map 2000 is transformed and distributed to each Winogradcompute tile (e.g., Winograd compute tile 1910A-1910M of FIG. 19) asneeded.

A Winograd input transform is used to calculate the Winograd transformof a given input feature map 2000. For F(4,3) Winograd convolution,input transform B^(T), shown above, is used. The transformation isperformed inline and the values of the input feature map 2000 can beaccessed in an overlapped manner. For example, for a given input featuremap 2000, a first 1×6 input feature map patch 2002 partially overlappingwith a second 1×6 input feature map 2004, which overlaps in part with athird 1×6 input feature map patch 2006.

FIG. 21 illustrates an architecture for a Winograd compute block 2100,according to an embodiment. The Winograd compute block 2100 is a versionof the Winograd compute blocks 1914A-1914N. The Winograd compute block2100 can accept as input 2102 a 1×6 transformed kernel and a 1×6transformed input patch. The input 2102 is processed by an array ofWinograd processing elements 2110 to generate a 1×6 output tensor 2104.The 1×6 output tensor 2104 is an untransformed output. An inverseWinograd transform can be applied to the output tensor 2104 to generatea 1×4 output tensor.

The illustrated array of processing element 2110 includes Six Winogradprocessing elements (e.g., Pe1 2112A through Pe6 2112F) to enable theelementwise multiply and accumulate operations for F(4,3) Winogradconvolution. However, the Winograd compute block 2100 may be scaledduring design phase for different forms of Winograd convolution. Anexemplary processing element (e.g. Pe6 2112F) includes a multiplier2122, an adder 2126, an accumulator register 2128, and a multiplexer2124. Each processing element 2112F can perform a multiply or an addoperation, as specified by commands provided by a Winograd controller,such as the Winograd controller 1922 of FIG. 19, and as illustrated inoperation 1710 of FIG. 17. Partial output feature map data 2130 (Y_(n)as in FIG. 17) can be stored in the accumulator register 2128 and outputto memory (e.g., output local memory 1916 of FIG. 19). Previous partialoutput feature map data 2118 (Y_(n_Prev) as in FIG. 17) can be read frommemory as specified by the Winograd controller 1922.

For each input feature map fetched from memory, the Winograd computearchitecture described herein, in one embodiment, performs calculationfor multiple output feature maps before fetching the next input featuremap. The number of output feature maps being computed in paralleldepends on number of processing tiles. The Winograd compute architecturedescribed herein can be used to implement a compute accelerator that canbe designed for used with any input memory size and can be configurablefor different market segments depending on the area budget. For example,accelerators that are targeted at training or inferencing can bedesigned. The resulting accelerator can provide as much as a 2× increasein performance relative to other neural network compute solutions. Invarious embodiments the architecture can be implemented in various typesof compute units, including general purpose graphics processors (e.g.,GPGPUs), field programmable gate arrays (FPGA), and hybrid acceleratorsusing a variety of different types of compute units.

Bandwidth Optimized Hardware to Compute Winograd Kernel Transforms

The transformations for the input and output data for Winogradconvolution are relatively cheap from a computational perspective, asthese transforms have compute requirements of the order O(N). However,Kernel/weight transforms are order O(N²) and generally require costlydivision operations. As kernels are known in advance, it may be possibleto perform the kernel transforms offline and use the transformed Kernelsduring the compute. However, this offline kernel transforms increasesthe memory bandwidth requirement of the system, as the transformedkernels are larger in size. For example, in the case of a 3×3 Kernel,the bandwidth requirement doubles. In case of a 5×5 kernel, thetransform increases the bandwidth by 240%.

Embodiments descried herein provide hardware logic to enable optimizedkernel/weight transforms for Winograd convolution. The hardware logicenable an optimized Winograd compute architecture reduces the complexityof in-line kernel transformations without significantly increasinghardware resource and memory bandwidth requirements. The optimizedkernel/weight transform allows simplified hardware logic, in that theoptimized transforms do not require hardware devisors that wouldotherwise be used for inline weight transformation and do not increasebandwidth requirements, as with offline weight transformation. Thetechniques described herein are computationally accurate and do notresult in any reduction in accuracy. Such techniques may be particularlysuited for inference optimized hardware, which is generally embeddedhardware in which performance per watt or performance per area are ofparticular importance.

One embodiment provides hardware logic that enables the kerneltransformation to be split into multiple phases. The first phaseincludes a division operation, which can be performed offline withoutincreasing memory bandwidth requirements, as the size of the kernelsafter the first transform phase is the same as the original kernels. Thesecond phase can be performed inline to general the final transformedweights. The second phase of the transform is done in-line with thecompute operations using only addition operations, without resulting anincrease in memory bandwidth requirements.

In one embodiment, Winograd convolution is performed using an F(4,3)transform, which uses the kernel transform G, which is described above,and also shown below:

$G = \begin{bmatrix}{1/4} & 0 & 0 \\{{- 1}/6} & {{- 1}/6} & {{- 1}/6} \\{{- 1}/6} & {1/6} & {{- 1}/6} \\{1/24} & {1/12} & {1/6} \\{1/24} & {{- 1}/12} & {1/6} \\0 & 0 & 1\end{bmatrix}$

The kernel transform matrix consists of division by 6, 12 and 24 whichare not easy to implement in hardware without consuming costly hardwareresources. Accordingly, the weight transformation is modified into G′,as shown below:

$G^{\prime} = {1/{3\mspace{11mu}\begin{bmatrix}{3/4} & 0 & 0 \\{{- 1}/2} & {{- 1}/2} & {{- 1}/2} \\{{- 1}/2} & {1/2} & {{- 1}/2} \\{1/8} & {1/4} & {1/2} \\{1/8} & {{- 1}/4} & {1/2} \\0 & 0 & 1\end{bmatrix}}}$

The first phase of the transform can be performed offline as adivide-by-three operation on the pre-transformed kernel data. Theoffline transformed weights can then be stored in system memory. Theremaining scaling and addition transformation operations of the secondphase can be performed in-line during convolution by weight transformlogic (e.g., weight transform logic 1911 of FIG. 19) using a modifiedsecond phase weight transform.

FIG. 22 illustrates logic configurable to perform native and optimizedweight transformation. Transformations can be performed on input weights2202 via a weight transform unit 2204 to generate a set of outputweights 2206. The tables below show Native Winograd weight transformscontrasted with the optimized Weight transforms provided by embodimentsdescribed herein. For a given pre-transformed kernel K having elements[k₀, k₁, k₂], a native Winograd weight transform can be performed usinga weight transform configured as in Table 1 below:

TABLE 1 Native F(4, 3) Winograd weight transform K′₀ = K₀ >> 2 K′₁ =−(K₀ + K₁ + K₂)/6 K′₂ = (K₁ − K₀ − K₂)/6 K′₃ = (K₀ + 2K₁ + 4K₂)/24 K′₄ =(K₀ − 2K₁ + 4K₂)/24 K′₅ = K₃

One embodiment described herein uses a modified kernel transform basedon offline transformed kernel k_(m) having elements

$\left\lbrack {{{k\; m_{0}} = \frac{k_{0}}{3}},{{km_{1}} = \frac{k_{1}}{3}},{{km_{2}} = \frac{k_{2}}{3}}} \right\rbrack,$

where the in-line transformation is configured as shown in Table 2below.

TABLE 2 Optimized F(4, 3) Winograd weight transform K′₀ = ((Km₀ << 1) +Km₀) >> 2 K′₁ = −(Km₀ + Km₁ + Km₂) >> 1 K′₂ = (Km₁ − Km₀ − Km₂) >> 1 K′₃= (Km₀ + (Km₁ << 1) + (Km₂ << 2)) >> 3 K′₄ = (Km₀ − (Km₁ << 1) + (Km₂ <<2)) >> 3 K′₅ = (Km₂ << 1) + Km₂

Using the in-line transform shown in Table 2, the weight transform logicwithin a Winograd compute accelerator can be implemented usingsignificantly reduced hardware logic complexity, resulting in areduction in power and/or area of an optimized weight transform unitrelative to a standard, un-optimized weight transform unit. The weighttransform described herein can be further optimized by re-using addersto perform the computations for different weights.

FIG. 23 illustrates an optimized Winograd weight transform architecture2300, according to an embodiment. The illustrated architecture 2300 useseight adders 2310A-2310H per weight transform. For fixed pointaccelerators, such implementation may be more efficient in area and/orpower compared to using divisor logic units, as the cost scales with thenumber of operations being performed (e.g., computing multiple outputfeature maps in parallel). The optimization provided by one embodimentallows the sharing of inputs and stacking of outputs from certainadders, to enable the weight transform shown in Table 2 to be performedusing a reduced number of logic units.

The optimized hardware provides five inputs into the eight adders2310A-2310H to generate six transformed kernel elements. A first input2301 ([Km₀<<1], [Km₀]) is provided to the first adder 2310A to generatea first intermediate output Y₀. The first intermediate output Y₀ isright shifted to generate a first transformed kernel element 2321([K′₀=Y₀>>2]). A second input ([Km₀], [Km₂]) 2302 is provided to asecond adder 2310B. The output of the second adder 2310B is provided tothe third adder 2310C and the fourth adder 2310D. A third input 2303([Km₁], [Km₁<<1]) is provided to the third through sixth adder2310C-2310F, with input element [Km₁] provided to the third and fourthadder 2310C-2310D and input element [Km₁<<1] provided to the fifth andsixth adder 2310E-2310C. The third adder 2310C outputs a secondintermediate value Y₁, which is transformed into a second output element2322 ([K′₁=Y₁>>1]). The fourth adder 2310D outputs a third intermediatevalue Y₂, which is transformed into a third output element 2323([K′₂=Y₂>>1]). The fifth adder 2310E outputs a third intermediate valueY₃, which is transformed into a fourth output element 2325([K′₃=Y₃>>3]). The sixth adder 2310F outputs a fourth intermediate valueY₄, which is transformed into a fifth output element 2325 ([K′₄=Y₄>>3]).The fifth adder 2310E and sixth adder 2310F receive output from theseventh adder 2310G, the seventh adder receiving a fourth input 2304([Km₀], [Km₂<<2]). A fifth input 2305 ([Km₂], [Km₂<<1]) is provided tothe eight adder 2310H, which generates a fifth intermediate output Y₅,which is used, without transform, as the sixth output 2326 ([K′₅=Y₅]).

Described above, in various embodiments, is a hardware-based Winogradconvolution acceleration architecture that enables a single Winogradtransform method (e.g., F(4,3)) to be applied to kernels of multiplesizes and strides. The Winograd acceleration architecture includes aWinograd controller that exercises fine-grain control of Winogradprocessing elements to enable the Winograd convolution using multiplekernel sizes. The Winograd acceleration architecture also includessteering write logic that enables Winograd convolution for multipledifferent kernel strides. Shared input and output transform units withinthe Winograd acceleration architecture allow the transform cost to beamortized over a large number of parallel compute operations, reducingthe hardware complexity, power, and area requirements to implementhardware accelerated Winograd convolution.

Additional optimizations are described that enable reduced power/areaweight transformation for use during a Winograd transform. The optimizedweight transform performs a two-phase transform including an offlineportion and an on-line transform performed in-line with the Winogradcompute operations. The optimized weight transform techniques allow aWinograd convolution accelerator to be implemented with reduced powerand area requirements suitable for neural network inferenceaccelerators.

Software and Firmware Implemented Optimizations

The hardware design elements described herein can also be implementedusing software or firmware techniques to sequence compute operations ona Winograd accelerator having support for a single kernel size andkernel stride. Firmware executing on a microcontroller, such as agraphics microcontroller, can perform operations according to a processillustrated in FIG. 24.

As shown in FIG. 24, a process 2400 to perform hardware-based Winogradconvolution using kernels of multiple sizes, according to embodimentsdescribed herein, includes to decompose a higher-order convolutionkernel having a first kernel size into multiple sub-kernels having asecond kernel size, as shown at block 2402, and transform at least apatch of an input feature map and the multiple sub-kernels based on aWinograd transform associated with the second kernel size, as shown atblock 2404. The process 2400 additionally includes to perform multiplesuccessive Winograd convolution operations to generate a set of partialoutput feature maps as shown at block 2406, and accumulate the multiplepartial output feature maps into an output feature map, as shown atblock 2408. The process 2400 additionally includes to perform an inverseWinograd transform on the output feature map to generate a transformedoutput feature map, as shown at block 2410.

Multi-stride Winograd convolution can be implemented by parsing andpacking kernel and feature map data and contiguously storing the kerneland feature map data into buffers based on the specified kernel strideof the convolution. An exemplary process is illustrated in FIG. 25.

As shown in FIG. 25, a process 2500 to perform hardware-based Winogradconvolution using kernels of multiple strides, according to embodimentsdescribed herein, includes to load kernel data and input feature mapdata into memory (e.g., system memory), where the kernel data andfeature map data to be processed via a hardware-based Winogradconvolution accelerator, as shown at block 2502. Software, firmware, orhardware logic can then write the kernel data and at least a patch ofthe input feature map data into a first (e.g., kernel) buffer and asecond (e.g., input) buffer, the write performed using steering writelogic to pack multiple portions of the input buffer and kernel bufferaccording to a specified kernel stride, as shown at block 2504. MultipleWinograd convolution passes can then be performed using data in thefirst buffer and the second buffer, as shown at block 2506. Intermediateoutput of the convolution passes can be accumulated at block 2508 beforean inverse Winograd transformation is performed on the intermediateoutput to generate a transformed output feature map at bock 2510.

Optimized kernel weight transformation can also be implemented insoftware or firmware of a data processing system, in an independentmanner from the other techniques described herein. For example, theweight transformation operations for a Winograd kernel transform can bedivided into multiple phases, including one or more offline transformphases and an online transform that is performed in-line with theWinograd compute operations. The one or more offline transformationsperform operations that are computationally more expensive to implementin hardware relative to the online portion of the transform.

In one embodiment, as shown in process 2600 of FIG. 26, a first (e.g.,offline) phase of the optimized Winograd kernel weight transformationcan be performed, where the first phase includes one or more paralleldivision operations on weight data to be transformed, as shown at block2602. The process 2600 additionally includes to write the output of thefirst phase of the multi-phase Winograd kernel transformation to memorythat is accessible by a hardware-based Winograd convolution accelerator,as shown at block 2604. The process 2600 additionally includes toperform a second phase of the multi-phase Winograd kernel transformationin-line with a Winograd convolution operation using hardware adder andshift logic, as shown at block 2606. The process 2600 additionallyincludes to perform at least a portion of a Winograd convolutionoperation using output from the second phase of the multi-phase Winogradkernel transformation, as shown at block 2608.

The second, online phase of the Winograd kernel transformation can beperformed using only adders and shifters, which are simpler to implementin hardware relative to divisor logic that is required for use by thefirst phase. The offline phase can be performed by general purposecomputation hardware in response to instructions provided by software orfirmware. For example, a machine learning framework can perform thedivision operations on the weight data before the weight data is provideto a Winograd convolution accelerator, which can perform the onlinetransformation portion in-line with the Winograd convolution. Furtheroptimization can be performed in the hardware portion of the weighttransformation logic that performs the online weight transforms. Thehardware weight transformation logic can be configured such thatmultiple adders are shared between multiple inputs, and one or more ofthe shared adders are used to generate multiple transformed kernelelements.

Machine Learning Overview

A machine learning algorithm is an algorithm that can learn based on aset of data. Embodiments of machine learning algorithms can be designedto model high-level abstractions within a data set. For example, imagerecognition algorithms can be used to determine which of severalcategories to which a given input belong; regression algorithms canoutput a numerical value given an input; and pattern recognitionalgorithms can be used to generate translated text or perform text tospeech and/or speech recognition.

An exemplary type of machine learning algorithm is a neural network.There are many types of neural networks; a simple type of neural networkis a feedforward network. A feedforward network may be implemented as anacyclic graph in which the nodes are arranged in layers. Typically, afeedforward network topology includes an input layer and an output layerthat are separated by at least one hidden layer. The hidden layertransforms input received by the input layer into a representation thatis useful for generating output in the output layer. The network nodesare fully connected via edges to the nodes in adjacent layers, but thereare no edges between nodes within each layer. Data received at the nodesof an input layer of a feedforward network are propagated (i.e., “fedforward”) to the nodes of the output layer via an activation functionthat calculates the states of the nodes of each successive layer in thenetwork based on coefficients (“weights”) respectively associated witheach of the edges connecting the layers. Depending on the specific modelbeing represented by the algorithm being executed, the output from theneural network algorithm can take various forms.

Before a machine learning algorithm can be used to model a particularproblem, the algorithm is trained using a training data set. Training aneural network involves selecting a network topology, using a set oftraining data representing a problem being modeled by the network, andadjusting the weights until the network model performs with a minimalerror for all instances of the training data set. For example, during asupervised learning training process for a neural network, the outputproduced by the network in response to the input representing aninstance in a training data set is compared to the “correct” labeledoutput for that instance, an error signal representing the differencebetween the output and the labeled output is calculated, and the weightsassociated with the connections are adjusted to minimize that error asthe error signal is backward propagated through the layers of thenetwork. The network is considered “trained” when the errors for each ofthe outputs generated from the instances of the training data set areminimized.

The accuracy of a machine learning algorithm can be affectedsignificantly by the quality of the data set used to train thealgorithm. The training process can be computationally intensive and mayrequire a significant amount of time on a conventional general-purposeprocessor. Accordingly, parallel processing hardware is used to trainmany types of machine learning algorithms. This is particularly usefulfor optimizing the training of neural networks, as the computationsperformed in adjusting the coefficients in neural networks lendthemselves naturally to parallel implementations. Specifically, manymachine learning algorithms and software applications have been adaptedto make use of the parallel processing hardware within general-purposegraphics processing devices.

FIG. 27 is a generalized diagram of a machine learning software stack2700. A machine learning application 2702 can be configured to train aneural network using a training dataset or to use a trained deep neuralnetwork to implement machine intelligence. The machine learningapplication 2702 can include training and inference functionality for aneural network and/or specialized software that can be used to train aneural network before deployment. The machine learning application 2702can implement any type of machine intelligence including but not limitedto image recognition, mapping and localization, autonomous navigation,speech synthesis, medical imaging, or language translation.

Hardware acceleration for the machine learning application 2702 can beenabled via a machine learning framework 2704. The machine learningframework 2704 can provide a library of machine learning primitives.Machine learning primitives are basic operations that are commonlyperformed by machine learning algorithms. Without the machine learningframework 2704, developers of machine learning algorithms would berequired to create and optimize the main computational logic associatedwith the machine learning algorithm, then re-optimize the computationallogic as new parallel processors are developed. Instead, the machinelearning application can be configured to perform the necessarycomputations using the primitives provided by the machine learningframework 2704. Exemplary primitives include tensor convolutions,activation functions, and pooling, which are computational operationsthat are performed while training a convolutional neural network (CNN).The machine learning framework 2704 can also provide primitives toimplement basic linear algebra subprograms performed by manymachine-learning algorithms, such as matrix and vector operations.

The machine learning framework 2704 can process input data received fromthe machine learning application 2702 and generate the appropriate inputto a compute framework 2706. The compute framework 2706 can abstract theunderlying instructions provided to the GPGPU driver 2708 to enable themachine learning framework 2704 to take advantage of hardwareacceleration via the GPGPU hardware 2710 without requiring the machinelearning framework 2704 to have intimate knowledge of the architectureof the GPGPU hardware 2710. Additionally, the compute framework 2706 canenable hardware acceleration for the machine learning framework 2704across a variety of types and generations of the GPGPU hardware 2710.

Machine Learning Neural Network Implementations

The computing architecture provided by embodiments described herein canbe configured to perform the types of parallel processing that isparticularly suited for training and deploying neural networks formachine learning. A neural network can be generalized as a network offunctions having a graph relationship. As is well-known in the art,there are a variety of types of neural network implementations used inmachine learning. One exemplary type of neural network is thefeedforward network, as previously described.

A second exemplary type of neural network is the Convolutional NeuralNetwork (CNN). A CNN is a specialized feedforward neural network forprocessing data having a known, grid-like topology, such as image data.Accordingly, CNNs are commonly used for compute vision and imagerecognition applications, but they also may be used for other types ofpattern recognition such as speech and language processing. The nodes inthe CNN input layer are organized into a set of “filters” (featuredetectors inspired by the receptive fields found in the retina), and theoutput of each set of filters is propagated to nodes in successivelayers of the network. The computations for a CNN include applying theconvolution mathematical operation to each filter to produce the outputof that filter. Convolution is a specialized kind of mathematicaloperation performed by two functions to produce a third function that isa modified version of one of the two original functions. Inconvolutional network terminology, the first function to the convolutioncan be referred to as the input, while the second function can bereferred to as the convolution kernel. The output may be referred to asthe feature map. For example, the input to a convolution layer can be amultidimensional array of data that defines the various color componentsof an input image. The convolution kernel can be a multidimensionalarray of parameters, where the parameters are adapted by the trainingprocess for the neural network.

Recurrent neural networks (RNNs) are a family of feedforward neuralnetworks that include feedback connections between layers. RNNs enablemodeling of sequential data by sharing parameter data across differentparts of the neural network. The architecture for a RNN includes cycles.The cycles represent the influence of a present value of a variable onits own value at a future time, as at least a portion of the output datafrom the RNN is used as feedback for processing subsequent input in asequence. This feature makes RNNs particularly useful for languageprocessing due to the variable nature in which language data can becomposed.

The figures described below present exemplary feedforward, CNN, and RNNnetworks, as well as describe a general process for respectivelytraining and deploying each of those types of networks. It will beunderstood that these descriptions are exemplary and non-limiting as toany specific embodiment described herein and the concepts illustratedcan be applied generally to deep neural networks and machine learningtechniques in general.

The exemplary neural networks described above can be used to performdeep learning. Deep learning is machine learning using deep neuralnetworks. The deep neural networks used in deep learning are artificialneural networks composed of multiple hidden layers, as opposed toshallow neural networks that include only a single hidden layer. Deeperneural networks are generally more computationally intensive to train.However, the additional hidden layers of the network enable multisteppattern recognition that results in reduced output error relative toshallow machine learning techniques.

Deep neural networks used in deep learning typically include a front-endnetwork to perform feature recognition coupled to a back-end networkwhich represents a mathematical model that can perform operations (e.g.,object classification, speech recognition, etc.) based on the featurerepresentation provided to the model. Deep learning enables machinelearning to be performed without requiring hand crafted featureengineering to be performed for the model. Instead, deep neural networkscan learn features based on statistical structure or correlation withinthe input data. The learned features can be provided to a mathematicalmodel that can map detected features to an output. The mathematicalmodel used by the network is generally specialized for the specific taskto be performed, and different models will be used to perform differenttask.

Once the neural network is structured, a learning model can be appliedto the network to train the network to perform specific tasks. Thelearning model describes how to adjust the weights within the model toreduce the output error of the network. Backpropagation of errors is acommon method used to train neural networks. An input vector ispresented to the network for processing. The output of the network iscompared to the desired output using a loss function and an error valueis calculated for each of the neurons in the output layer. The errorvalues are then propagated backwards until each neuron has an associatederror value which roughly represents its contribution to the originaloutput. The network can then learn from those errors using an algorithm,such as the stochastic gradient descent algorithm, to update the weightsof the of the neural network.

FIG. 28A-28B illustrate an exemplary convolutional neural network. FIG.28A illustrates various layers within a CNN. As shown in FIG. 28A, anexemplary CNN used to model image processing can receive input 2802describing the red, green, and blue (RGB) components of an input image.The input 2802 can be processed by multiple convolutional layers (e.g.,convolutional layer 2804, convolutional layer 2806). The output from themultiple convolutional layers may optionally be processed by a set offully connected layers 2808. Neurons in a fully connected layer havefull connections to all activations in the previous layer, as previouslydescribed for a feedforward network. The output from the fully connectedlayers 2808 can be used to generate an output result from the network.The activations within the fully connected layers 2808 can be computedusing matrix multiplication instead of convolution. Not all CNNimplementations are make use of fully connected layers DPLA08. Forexample, in some implementations the convolutional layer 2806 cangenerate output for the CNN.

The convolutional layers are sparsely connected, which differs fromtraditional neural network configuration found in the fully connectedlayers 2808. Traditional neural network layers are fully connected, suchthat every output unit interacts with every input unit. However, theconvolutional layers are sparsely connected because the output of theconvolution of a field is input (instead of the respective state valueof each of the nodes in the field) to the nodes of the subsequent layer,as illustrated. The kernels associated with the convolutional layersperform convolution operations, the output of which is sent to the nextlayer. The dimensionality reduction performed within the convolutionallayers is one aspect that enables the CNN to scale to process largeimages.

FIG. 28B illustrates exemplary computation stages within a convolutionallayer of a CNN. Input to a convolutional layer 2812 of a CNN can beprocessed in three stages of a convolutional layer 2814. The threestages can include a convolution stage 2816, a detector stage 2818, anda pooling stage 2820. The convolution layer 2814 can then output data toa successive convolutional layer. The final convolutional layer of thenetwork can generate output feature map data or provide input to a fullyconnected layer, for example, to generate a classification value for theinput to the CNN.

In the convolution stage 2816 performs several convolutions in parallelto produce a set of linear activations. The convolution stage 2816 caninclude an affine transformation, which is any transformation that canbe specified as a linear transformation plus a translation. Affinetransformations include rotations, translations, scaling, andcombinations of these transformations. The convolution stage computesthe output of functions (e.g., neurons) that are connected to specificregions in the input, which can be determined as the local regionassociated with the neuron. The neurons compute a dot product betweenthe weights of the neurons and the region in the local input to whichthe neurons are connected. The output from the convolution stage 2816defines a set of linear activations that are processed by successivestages of the convolutional layer 2814.

The linear activations can be processed by a detector stage 2818. In thedetector stage 2818, each linear activation is processed by a non-linearactivation function. The non-linear activation function increases thenonlinear properties of the overall network without affecting thereceptive fields of the convolution layer. Several types of non-linearactivation functions may be used. One particular type is the rectifiedlinear unit (ReLU), which uses an activation function defined asƒ(x)=max (0, x), such that the activation is thresholded at zero.

The pooling stage 2820 uses a pooling function that replaces the outputof the convolutional layer 2806 with a summary statistic of the nearbyoutputs. The pooling function can be used to introduce translationinvariance into the neural network, such that small translations to theinput do not change the pooled outputs. Invariance to local translationcan be useful in scenarios where the presence of a feature in the inputdata is more important than the precise location of the feature. Varioustypes of pooling functions can be used during the pooling stage 2820,including max pooling, average pooling, and 12-norm pooling.Additionally, some CNN implementations do not include a pooling stage.Instead, such implementations substitute and additional convolutionstage having an increased stride relative to previous convolutionstages.

The output from the convolutional layer 2814 can then be processed bythe next layer 2822. The next layer 2822 can be an additionalconvolutional layer or one of the fully connected layers 2808. Forexample, the first convolutional layer 2804 of FIG. 28A can output tothe second convolutional layer 2806, while the second convolutionallayer can output to a first layer of the fully connected layers 2808.

FIG. 29 illustrates an exemplary recurrent neural network 2900. In arecurrent neural network (RNN), the previous state of the networkinfluences the output of the current state of the network. RNNs can bebuilt in a variety of ways using a variety of functions. The use of RNNsgenerally revolves around using mathematical models to predict thefuture based on a prior sequence of inputs. For example, an RNN may beused to perform statistical language modeling to predict an upcomingword given a previous sequence of words. The illustrated RNN 2900 can bedescribed has having an input layer 2902 that receives an input vector,hidden layers 2904 to implement a recurrent function, a feedbackmechanism 2905 to enable a ‘memory’ of previous states, and an outputlayer 2906 to output a result. The RNN 2900 operates based ontime-steps. The state of the RNN at a given time step is influencedbased on the previous time step via the feedback mechanism 2905. For agiven time step, the state of the hidden layers 2904 is defined by theprevious state and the input at the current time step. An initial input(x₁) at a first time step can be processed by the hidden layer 2904. Asecond input (x₂) can be processed by the hidden layer 2904 using stateinformation that is determined during the processing of the initialinput (x₁). A given state can be computed as s_(t)=ƒ(Ux_(t)+Ws_(t-1)),where U and W are parameter matrices. The function ƒ is generally anonlinearity, such as the hyperbolic tangent function (Tan h) or avariant of the rectifier function ƒ(x)=max(0, x). However, the specificmathematical function used in the hidden layers 2904 can vary dependingon the specific implementation details of the RNN 2900.

In addition to the basic CNN and RNN networks described, variations onthose networks may be enabled. One example RNN variant is the long shortterm memory (LSTM) RNN. LSTM RNNs are capable of learning long-termdependencies that may be necessary for processing longer sequences oflanguage. A variant on the CNN is a convolutional deep belief network,which has a structure similar to a CNN and is trained in a mannersimilar to a deep belief network. A deep belief network (DBN) is agenerative neural network that is composed of multiple layers ofstochastic (random) variables. DBNs can be trained layer-by-layer usinggreedy unsupervised learning. The learned weights of the DBN can then beused to provide pre-train neural networks by determining an optimalinitial set of weights for the neural network.

FIG. 30 illustrates training and deployment of a deep neural network.Once a given network has been structured for a task the neural networkis trained using a training dataset 3002. Various training frameworks3004 have been developed to enable hardware acceleration of the trainingprocess. For example, the machine learning framework 2704 of FIG. 27 maybe configured as a training framework 2704. The training framework 2704can hook into an untrained neural network 3006 and enable the untrainedneural net to be trained using the parallel processing resourcesdescribed herein to generate a trained neural net 3008.

To start the training process the initial weights may be chosen randomlyor by pre-training using a deep belief network. The training cycle thenbe performed in either a supervised or unsupervised manner.

Supervised learning is a learning method in which training is performedas a mediated operation, such as when the training dataset 3002 includesinput paired with the desired output for the input, or where thetraining dataset includes input having known output and the output ofthe neural network is manually graded. The network processes the inputsand compares the resulting outputs against a set of expected or desiredoutputs. Errors are then propagated back through the system. Thetraining framework 3004 can adjust to adjust the weights that controlthe untrained neural network 3006. The training framework 3004 canprovide tools to monitor how well the untrained neural network 3006 isconverging towards a model suitable to generating correct answers basedon known input data. The training process occurs repeatedly as theweights of the network are adjusted to refine the output generated bythe neural network. The training process can continue until the neuralnetwork reaches a statistically desired accuracy associated with atrained neural net 3008. The trained neural network 3008 can then bedeployed to implement any number of machine learning operations.

Unsupervised learning is a learning method in which the network attemptsto train itself using unlabeled data. Thus, for unsupervised learningthe training dataset 3002 will include input data without any associatedoutput data. The untrained neural network 3006 can learn groupingswithin the unlabeled input and can determine how individual inputs arerelated to the overall dataset. Unsupervised training can be used togenerate a self-organizing map, which is a type of trained neuralnetwork 3007 capable of performing operations useful in reducing thedimensionality of data. Unsupervised training can also be used toperform anomaly detection, which allows the identification of datapoints in an input dataset that deviate from the normal patterns of thedata.

Variations on supervised and unsupervised training may also be employed.Semi-supervised learning is a technique in which in the training dataset3002 includes a mix of labeled and unlabeled data of the samedistribution. Incremental learning is a variant of supervised learningin which input data is continuously used to further train the model.Incremental learning enables the trained neural network 3008 to adapt tothe new data 3012 without forgetting the knowledge instilled within thenetwork during initial training.

Whether supervised or unsupervised, the training process forparticularly deep neural networks may be too computationally intensivefor a single compute node. Instead of using a single compute node, adistributed network of computational nodes can be used to accelerate thetraining process.

FIG. 31 is a block diagram illustrating distributed learning.Distributed learning is a training model that uses multiple distributedcomputing nodes to perform supervised or unsupervised training of aneural network. The distributed computational nodes can each include oneor more host processors and one or more of the general-purposeprocessing nodes, such as the highly-parallel general-purpose graphicsprocessing unit 2800 as in FIG. 2800. As illustrated, distributedlearning can be performed model parallelism 3102, data parallelism 3104,or a combination of model and data parallelism 3104.

In model parallelism 3102, different computational nodes in adistributed system can perform training computations for different partsof a single network. For example, each layer of a neural network can betrained by a different processing node of the distributed system. Thebenefits of model parallelism include the ability to scale toparticularly large models. Splitting the computations associated withdifferent layers of the neural network enables the training of verylarge neural networks in which the weights of all layers would not fitinto the memory of a single computational node. In some instances, modelparallelism can be particularly useful in performing unsupervisedtraining of large neural networks.

In data parallelism 3104, the different nodes of the distributed networkhave a complete instance of the model and each node receives a differentportion of the data. The results from the different nodes are thencombined. While different approaches to data parallelism are possible,data parallel training approaches all require a technique of combiningresults and synchronizing the model parameters between each node.Exemplary approaches to combining data include parameter averaging andupdate based data parallelism. Parameter averaging trains each node on asubset of the training data and sets the global parameters (e.g.,weights, biases) to the average of the parameters from each node.Parameter averaging uses a central parameter server that maintains theparameter data. Update based data parallelism is similar to parameteraveraging except that instead of transferring parameters from the nodesto the parameter server, the updates to the model are transferred.Additionally, update based data parallelism can be performed in adecentralized manner, where the updates are compressed and transferredbetween nodes.

Combined model and data parallelism 3106 can be implemented, forexample, in a distributed system in which each computational nodeincludes multiple GPUs. Each node can have a complete instance of themodel with separate GPUs within each node are used to train differentportions of the model.

Distributed training has increased overhead relative to training on asingle machine. However, the parallel processors and GPGPUs describedherein can each implement various techniques to reduce the overhead ofdistributed training, including techniques to enable high bandwidthGPU-to-GPU data transfer and accelerated remote data synchronization.

Exemplary Machine Learning Applications

Machine learning can be applied to solve a variety of technologicalproblems, including but not limited to computer vision, autonomousdriving and navigation, speech recognition, and language processing.Computer vision has traditionally been one of the most active researchareas for machine learning applications. Applications of computer visionrange from reproducing human visual abilities, such as recognizingfaces, to creating new categories of visual abilities. For example,computer vision applications can be configured to recognize sound wavesfrom the vibrations induced in objects visible in a video. Parallelprocessor accelerated machine learning enables computer visionapplications to be trained using significantly larger training datasetthan previously feasible and enables inferencing systems to be deployedusing low power parallel processors.

Parallel processor accelerated machine learning has autonomous drivingapplications including lane and road sign recognition, obstacleavoidance, navigation, and driving control. Accelerated machine learningtechniques can be used to train driving models based on datasets thatdefine the appropriate responses to specific training input. Theparallel processors described herein can enable rapid training of theincreasingly complex neural networks used for autonomous drivingsolutions and enables the deployment of low power inferencing processorsin a mobile platform suitable for integration into autonomous vehicles.

Parallel processor accelerated deep neural networks have enabled machinelearning approaches to automatic speech recognition (ASR). ASR includesthe creation of a function that computes the most probable linguisticsequence given an input acoustic sequence. Accelerated machine learningusing deep neural networks have enabled the replacement of the hiddenMarkov models (HMMs) and Gaussian mixture models (GMMs) previously usedfor ASR.

Parallel processor accelerated machine learning can also be used toaccelerate natural language processing. Automatic learning procedurescan make use of statistical inference algorithms to produce models thatare robust to erroneous or unfamiliar input. Exemplary natural languageprocessor applications include automatic machine translation betweenhuman languages.

The parallel processing platforms used for machine learning can bedivided into training platforms and deployment platforms. Trainingplatforms are generally highly parallel and include optimizations toaccelerate multi-GPU single node training and multi-node, multi-GPUtraining. Exemplary parallel processors suited for training include thehighly-parallel general-purpose graphics processing unit 2800 of FIG.2800 and the multi-GPU computing system 2900 of FIG. 2900. On thecontrary, deployed machine learning platforms generally include lowerpower parallel processors suitable for use in products such as cameras,autonomous robots, and autonomous vehicles.

The following clauses and/or examples pertain to specific embodiments orexamples thereof. Specifics in the examples may be used anywhere in oneor more embodiments. The various features of the different embodimentsor examples may be variously combined with some features included andothers excluded to suit a variety of different applications. Examplesmay include subject matter such as a method, means for performing actsof the method, at least one machine-readable medium includinginstructions that, when performed by a machine cause the machine toperform acts of the method, or of an apparatus or system according toembodiments and examples described herein. Various components can be ameans for performing the operations or functions described.

One embodiment provides a compute apparatus to perform machine learningoperations, the compute apparatus comprising a hardware acceleratorincluding a compute unit to perform a Winograd convolution, the computeunit configurable to perform the Winograd convolution for a first kernelsize using a transform associated with a second kernel size.

In one embodiment the hardware accelerator includes a register to storea value for the second kernel size, the second kernel size configurablevia an interface to the register, the interface to the register providedby the hardware accelerator. The hardware accelerator can include acontrol unit to provide an instruction to the compute unit, theinstruction to cause the compute unit to perform a Winograd convolutionoperation based on the value for the second kernel size. In oneembodiment the hardware accelerator includes steering write logic toenable Winograd convolution for multiple different kernel strides. Inone embodiment the compute unit is configurable to perform the Winogradconvolution for a first kernel stride using a transform associated witha second kernel stride. In one embodiment the hardware acceleratorincluding a register to store a value of the second kernel stride andthe steering write logic is to write input data and kernel data tomemory within the hardware accelerator according to the value of thesecond kernel stride.

In one embodiment the hardware accelerator includes multiple tiles ofcompute logic, each tile including multiple compute units. Each of themultiple tiles of compute logic can include a weight transform unit toapply a Winograd transform to weights associated with a convolutionkernel and store transformed weights to a memory coupled with the weighttransform unit. The transformed weights can be stored to the memory thatis coupled with the weight transform unit shared among the multiplecompute units within the tile of compute logic including the weighttransform unit and the memory coupled with the weight transform unit. Inone embodiment the hardware accelerator includes an input transform unitconfigured to apply a Winograd transform to input feature map data, theinput transform unit shared between the multiple tiles of compute logic.

One embodiment provides for a method of performing machine learningoperations, the method comprising decomposing a convolution kernelhaving a first kernel size into multiple sub-kernels having a secondkernel size; transforming a portion of an input feature map and themultiple sub-kernels based on a Winograd transform, the Winogradtransform associated with the second kernel size; and performingmultiple successive Winograd convolution operations to generate a set ofpartial output feature maps.

In one embodiment the method additionally includes accumulating multiplepartial output feature maps into an output feature map; and performingan inverse Winograd transform on the output feature map to generate atransformed output feature map. In one embodiment, performing themultiple successive Winograd convolution operations to generate a set ofpartial output feature maps includes loading kernel data and inputfeature map data into memory, the kernel data and input feature map datato be processed via a hardware-based Winograd convolution accelerator;writing the kernel data to a first hardware buffer; writing at least aportion of the input feature map data into a second hardware buffer;performing multiple successive Winograd convolution passes via thehardware-based Winograd convolution accelerator using data in the firsthardware buffer and the second hardware buffer; accumulatingintermediate output of the multiple successive Winograd convolutionpasses; and performing an inverse Winograd transform on the intermediateoutput to generate a transformed output feature map.

In one embodiment, transforming a portion of a sub-kernel based on aWinograd transform includes performing a first phase of a multi-phaseWinograd kernel transformation, the first phase including one or moreparallel division operations; and performing a second phase of themulti-phase Winograd kernel transformation, the second phase performedin-line with a Winograd convolution operation using hardware adder andshift logic. In one embodiment the method additionally includesperforming at least a portion of a Winograd convolution operation usingoutput from the second phase of the multi-phase Winograd kerneltransformation.

One embodiment provides for a data processing system comprising anon-transitory machine-readable medium to store instructions forexecution by one or more processors of the data processing system and ageneral-purpose graphics processing unit including a hardwareaccelerator including a compute unit to perform a Winograd convolution,the compute unit configurable to perform the Winograd convolution for afirst kernel size using a transform associated with a second kernelsize. The compute unit of the data processing system can perform any ofthe Winograd convolution operations otherwise described herein.

The embodiments described herein refer to specific configurations ofhardware, such as application specific integrated circuits (ASICs),configured to perform certain operations or having a predeterminedfunctionality. Embodiments described herein may also be incorporatedinto hardware products such as, but not limited to, FPGA, CPU, or GPUbased computer vision accelerators. The hardware and/or softwaretechniques can be applied to various Internet of things (IoT) solutionsincluding autonomous driving, autonomous robots, and computer visionsystems for augmented reality and/or virtual reality. Such electronicdevices typically include a set of one or more processors coupled to oneor more other components, such as one or more storage devices(non-transitory machine-readable storage media), user input/outputdevices (e.g., a keyboard, a touchscreen, and/or a display), and networkconnections. The coupling of the set of processors and other componentsis typically through one or more busses and bridges (also termed as buscontrollers). The storage device and signals carrying the networktraffic respectively represent one or more machine-readable storagemedia and machine-readable communication media. Thus, the storagedevices of a given electronic device typically store code and/or datafor execution on the set of one or more processors of that electronicdevice. Furthermore, some elements may be incorporated intosoftware-based machine learning acceleration frameworks.

Of course, one or more parts of an embodiment may be implemented usingdifferent combinations of software, firmware, and/or hardware.Throughout this detailed description, for the purposes of explanation,numerous specific details were set forth in order to provide a thoroughunderstanding of the present invention. It will be apparent, however, toone skilled in the art that the embodiments may be practiced withoutsome of these specific details. In certain instances, well-knownstructures and functions were not described in elaborate detail to avoidobscuring the inventive subject matter of the embodiments. Accordingly,the scope and spirit of the invention should be judged in terms of theclaims that follow.

1.-20. (canceled)
 21. An apparatus to perform machine learningoperations, the apparatus comprising: a hardware accelerator to performa convolution operation associated with a first kernel based on atransform associated with a second kernel.
 22. The apparatus of claim21, wherein the convolution operation comprises a Winograd convolutionoperation, and wherein the transform comprises a Winograd transform. 23.The apparatus of claim 21, wherein the hardware accelerator comprisesone or more registers to store one or more values associated with thefirst and second kernels.
 24. The apparatus of claim 21, wherein thehardware accelerator is further to write input data and kernel data tomemory associated with the hardware accelerator.
 25. The apparatus ofclaim 21, wherein the convolution operation is performed for multiplekernel strides associated with the first and second kernels.
 26. Amethod comprising: performing, by a hardware accelerator of a computingdevice, a convolution operation associated with a first kernel based ona transform associated with a second kernel.
 27. The method of claim 26,wherein the convolution operation comprises a Winograd convolutionoperation, and wherein the transform comprises a Winograd transform. 28.The method of claim 26, wherein the hardware accelerator comprises oneor more registers to store one or more values associated with the firstand second kernels.
 29. The method of claim 26, wherein the hardwareaccelerator is further to write input data and kernel data to memoryassociated with the hardware accelerator.
 30. The method of claim 26,wherein the convolution operation is performed for multiple kernelstrides associated with the first and second kernels.
 31. Acomputer-readable medium having stored thereon instructions which, whenexecuted, cause a computing device to perform operations comprising:performing, by a hardware accelerator of the computing device, aconvolution operation associated with a first kernel based on atransform associated with a second kernel.
 32. The computer-readablemedium of claim 31, wherein the convolution operation comprises aWinograd convolution operation, and wherein the transform comprises aWinograd transform.
 33. The computer-readable medium of claim 31,wherein the hardware accelerator comprises one or more registers tostore one or more values associated with the first and second kernels.34. The computer-readable medium of claim 31, wherein the hardwareaccelerator is further to write input data and kernel data to memoryassociated with the hardware accelerator.
 35. The computer-readablemedium of claim 31, wherein the convolution operation is performed formultiple kernel strides associated with the first and second kernels.